Commit 0e0779da authored by Lorenzo Pieralisi's avatar Lorenzo Pieralisi Committed by Russell King

ARM: 8053/1: kernel: sleep: restore HYP mode configuration in cpu_resume

On CPUs with virtualization extensions the kernel installs HYP mode
configuration on both primary and secondary cpus upon cold boot.

On platforms where CPUs are shutdown in idle paths (ie CPU core gating),
when a CPU resumes from low-power states it currently does not execute
code that reinstalls the HYP configuration, which means that the kernel
cannot run eg KVM properly on such machines.

This patch, mirroring cold-boot behaviour, executes position independent
code that reinstalls HYP configuration and drops to SVC mode safely on
warmboot, so that deep idle states can be enabled in kernel running as
hosts on platforms with power management HW.

Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Dave Martin <dave.martin@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Nicolas Pitre <nico@linaro.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Reviewed-by: default avatarDave Martin <Dave.Martin@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 72e6ae28
...@@ -312,7 +312,7 @@ ...@@ -312,7 +312,7 @@
* you cannot return to the original mode. * you cannot return to the original mode.
*/ */
.macro safe_svcmode_maskall reg:req .macro safe_svcmode_maskall reg:req
#if __LINUX_ARM_ARCH__ >= 6 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
mrs \reg , cpsr mrs \reg , cpsr
eor \reg, \reg, #HYP_MODE eor \reg, \reg, #HYP_MODE
tst \reg, #MODE_MASK tst \reg, #MODE_MASK
......
...@@ -127,6 +127,10 @@ ENDPROC(cpu_resume_after_mmu) ...@@ -127,6 +127,10 @@ ENDPROC(cpu_resume_after_mmu)
.align .align
ENTRY(cpu_resume) ENTRY(cpu_resume)
ARM_BE8(setend be) @ ensure we are in BE mode ARM_BE8(setend be) @ ensure we are in BE mode
#ifdef CONFIG_ARM_VIRT_EXT
bl __hyp_stub_install_secondary
#endif
safe_svcmode_maskall r1
mov r1, #0 mov r1, #0
ALT_SMP(mrc p15, 0, r0, c0, c0, 5) ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
ALT_UP_B(1f) ALT_UP_B(1f)
...@@ -144,7 +148,6 @@ ARM_BE8(setend be) @ ensure we are in BE mode ...@@ -144,7 +148,6 @@ ARM_BE8(setend be) @ ensure we are in BE mode
ldr r0, [r0, #SLEEP_SAVE_SP_PHYS] ldr r0, [r0, #SLEEP_SAVE_SP_PHYS]
ldr r0, [r0, r1, lsl #2] ldr r0, [r0, r1, lsl #2]
setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off
@ load phys pgd, stack, resume fn @ load phys pgd, stack, resume fn
ARM( ldmia r0!, {r1, sp, pc} ) ARM( ldmia r0!, {r1, sp, pc} )
THUMB( ldmia r0!, {r1, r2, r3} ) THUMB( ldmia r0!, {r1, r2, r3} )
......
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