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Commit 0e5e5845 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'sti-dt-for-v4.2-2' of... 

Merge tag 'sti-dt-for-v4.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti into next/dt

Merge "STi DT updates for v4.2, round 2." from Maxime Coquelin:

Highlights:
-----------
 - Add USB3 support to STiH410 & STiH418
 - Add PWM support to STiH416 & STiH407 family
 - Add restart support to STiH416 & STiH407 family
 - Add PMU support to STiH416 & STiH407 family
 - Reorder includes in STiH407 DT files

* tag 'sti-dt-for-v4.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti:
  ARM: STi: DT: STih407: Re-order #include <*.dtsi> files
  ARM: STi: Ensure requested STi's SysCfg Controlled IRQs are enabled at boot
  ARM: STi: STiH407: Enable PMU IRQs
  ARM: STi: STiH407: Enable Cortex-A9 PMU support
  ARM: STi: STiH416: Enable PMU IRQs
  ARM: STi: STiH416: Enable Cortex-A9 PMU support
  ARM: STi: STiH416: Add Restart support for STiH416
  ARM: STi: STiH407: Add Restart support for STiH407
  ARM: STi: STiH416-b2020e: Enable PWM on the B2020 Rev-E
  ARM: STi: STiH416: Add DT nodes for PWM
  ARM: STi: STiH416: Add Pinctrl settings for PWM
  ARM: STi: STiH407: Add DT nodes for for PWM
  ARM: DT: STi: STiH418: Enable USB3 port on stih418-b2199.
  ARM: DT: STi: STiH418: Add miphy28lp optional oscillator clock properties
  ARM: DT: STi: stihxxx-b2120: Enable USB3 port on stih407-b2120 and stih410-b2120
  ARM: DT: STi: STiH407: Add dwc3 usb3 DT node.
  ARM: DT: STi: STiH407: Update picophyreset for the usb3 controllers usb2 phy
parents d0d89bb6 2cdce7a9
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arch/arm/boot/dts/stih407-b2120.dts
View file @ 0e5e5845
......@@ -7,8 +7,8 @@
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "stihxxx-b2120.dtsi"
#include "stih407.dtsi"
#include "stihxxx-b2120.dtsi"
/ {
model = "STiH407 B2120";
compatible = "st,stih407-b2120", "st,stih407";
......
arch/arm/boot/dts/stih407-family.dtsi
View file @ 0e5e5845
......@@ -10,6 +10,7 @@
#include <dt-bindings/mfd/st-lpc.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset-controller/stih407-resets.h>
#include <dt-bindings/interrupt-controller/irq-st.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
......@@ -58,6 +59,12 @@ l2: cache-controller {
cache-level = <2>;
};
arm-pmu {
interrupt-parent = <&intc>;
compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
......@@ -65,6 +72,12 @@ soc {
ranges;
compatible = "simple-bus";
restart {
compatible = "st,stih407-restart";
st,syscfg = <&syscfg_sbc_reg>;
status = "okay";
};
powerdown: powerdown-controller {
compatible = "st,stih407-powerdown";
#reset-cells = <1>;
......@@ -115,6 +128,15 @@ syscfg_lpm: lpm-syscfg@94b5100 {
reg = <0x94b5100 0x1000>;
};
irq-syscfg {
compatible = "st,stih407-irq-syscfg";
st,syscfg = <&syscfg_core>;
st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
<ST_IRQ_SYSCFG_PMU_1>;
st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
<ST_IRQ_SYSCFG_DISABLED>;
};
serial@9830000 {
compatible = "st,asc";
reg = <0x9830000 0x2c>;
......@@ -282,7 +304,7 @@ usb2_picophy0: phy1 {
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0x100 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
<&picophyreset STIH407_PICOPHY0_RESET>;
<&picophyreset STIH407_PICOPHY2_RESET>;
reset-names = "global", "port";
};
......@@ -516,5 +538,32 @@ sata1: sata@9b28000 {
status = "disabled";
};
st_dwc3: dwc3@8f94000 {
compatible = "st,stih407-dwc3";
reg = <0x08f94000 0x1000>, <0x110 0x4>;
reg-names = "reg-glue", "syscfg-reg";
st,syscfg = <&syscfg_core>;
resets = <&powerdown STIH407_USB3_POWERDOWN>,
<&softreset STIH407_MIPHY2_SOFTRESET>;
reset-names = "powerdown", "softreset";
#address-cells = <1>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3>;
ranges;
status = "disabled";
dwc3: dwc3@9900000 {
compatible = "snps,dwc3";
reg = <0x09900000 0x100000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
dr_mode = "host";
phy-names = "usb2-phy", "usb3-phy";
phys = <&usb2_picophy0>,
<&phy_port2 PHY_TYPE_USB3>;
};
};
};
};
arch/arm/boot/dts/stih407.dtsi
View file @ 0e5e5845
......@@ -147,5 +147,33 @@ sti-hda@8d02000 {
};
};
};
/* COMMS PWM Module */
pwm0: pwm@9810000 {
compatible = "st,sti-pwm";
status = "disabled";
#pwm-cells = <2>;
reg = <0x9810000 0x68>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
clock-names = "pwm";
clocks = <&clk_sysin>;
};
/* SBC PWM Module */
pwm1: pwm@9510000 {
compatible = "st,sti-pwm";
status = "disabled";
#pwm-cells = <2>;
reg = <0x9510000 0x68>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1_chan0_default
&pinctrl_pwm1_chan1_default
&pinctrl_pwm1_chan2_default
&pinctrl_pwm1_chan3_default>;
clock-names = "pwm";
clocks = <&clk_sysin>;
st,pwm-num-chan = <4>;
};
};
};
arch/arm/boot/dts/stih416-b2020e.dts
View file @ 0e5e5845
......@@ -51,5 +51,15 @@ phy_port1: port@fe38a000 {
sata0: sata@fe380000{
status = "okay";
};
/* SAS PWM Module */
pwm0: pwm@fed10000 {
status = "okay";
};
/* SBC PWM Module */
pwm1: pwm@fe510000 {
status = "okay";
};
};
};
arch/arm/boot/dts/stih416-pinctrl.dtsi
View file @ 0e5e5845
......@@ -216,6 +216,29 @@ st,pins {
};
};
};
pwm1 {
pinctrl_pwm1_chan0_default: pwm1-0-default {
st,pins {
pwm-out = <&pio3 0 ALT1 OUT>;
};
};
pinctrl_pwm1_chan1_default: pwm1-1-default {
st,pins {
pwm-out = <&pio4 4 ALT1 OUT>;
};
};
pinctrl_pwm1_chan2_default: pwm1-2-default {
st,pins {
pwm-out = <&pio4 6 ALT3 OUT>;
};
};
pinctrl_pwm1_chan3_default: pwm1-3-default {
st,pins {
pwm-out = <&pio4 7 ALT3 OUT>;
};
};
};
};
pin-controller-front {
......@@ -310,6 +333,14 @@ pio31: gpio@fee09000 {
st,bank-name = "PIO31";
};
pwm0 {
pinctrl_pwm0_chan0_default: pwm0-0-default {
st,pins {
pwm-out = <&pio9 7 ALT2 OUT>;
};
};
};
serial2-oe {
pinctrl_serial2_oe: serial2-1 {
st,pins {
......@@ -540,6 +571,25 @@ st,pins {
};
};
};
pwm0 {
pinctrl_pwm0_chan1_default: pwm0-1-default {
st,pins {
pwm-out = <&pio13 2 ALT2 OUT>;
};
};
pinctrl_pwm0_chan2_default: pwm0-2-default {
st,pins {
pwm-out = <&pio15 2 ALT4 OUT>;
};
};
pinctrl_pwm0_chan3_default: pwm0-3-default {
st,pins {
pwm-out = <&pio17 4 ALT1 OUT>;
};
};
};
};
pin-controller-fvdp-fe {
......
arch/arm/boot/dts/stih416.dtsi
View file @ 0e5e5845
......@@ -13,6 +13,7 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset-controller/stih416-resets.h>
#include <dt-bindings/interrupt-controller/irq-st.h>
/ {
L2: cache-controller {
compatible = "arm,pl310-cache";
......@@ -23,6 +24,12 @@ L2: cache-controller {
cache-level = <2>;
};
arm-pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
......@@ -30,6 +37,12 @@ soc {
ranges;
compatible = "simple-bus";
restart {
compatible = "st,stih416-restart";
st,syscfg = <&syscfg_sbc>;
status = "okay";
};
powerdown: powerdown-controller {
#reset-cells = <1>;
compatible = "st,stih416-powerdown";
......@@ -86,6 +99,15 @@ syscfg_lpm:lpm-syscfg@fe4b5100{
reg = <0xfe4b5100 0x8>;
};
irq-syscfg {
compatible = "st,stih416-irq-syscfg";
st,syscfg = <&syscfg_cpu>;
st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
<ST_IRQ_SYSCFG_PMU_1>;
st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
<ST_IRQ_SYSCFG_DISABLED>;
};
serial2: serial@fed32000{
compatible = "st,asc";
status = "disabled";
......@@ -104,7 +126,7 @@ sbc_serial1: serial@fe531000 {
interrupts = <0 210 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_serial1>;
clocks = <&clk_sysin>;
clocks = <&clk_sysin>;
};
i2c@fed40000 {
......@@ -445,5 +467,47 @@ ohci3: usb@fe343c00 {
<&softreset STIH416_USB3_SOFTRESET>;
reset-names = "power", "softreset";
};
/* SAS PWM Module */
pwm0: pwm@fed10000 {
compatible = "st,sti-pwm";
status = "disabled";
#pwm-cells = <2>;
reg = <0xfed10000 0x68>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_chan0_default
&pinctrl_pwm0_chan1_default
&pinctrl_pwm0_chan2_default
&pinctrl_pwm0_chan3_default>;
clock-names = "pwm";
clocks = <&clk_sysin>;
st,pwm-num-chan = <4>;
};
/* SBC PWM Module */
pwm1: pwm@fe510000 {
compatible = "st,sti-pwm";
status = "disabled";
#pwm-cells = <2>;
reg = <0xfe510000 0x68>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1_chan0_default
/*
* Shared with SBC_OBS_NOTRST. Don't
* enable unless you really know what
* you're doing.
*
* &pinctrl_pwm1_chan1_default
*/
&pinctrl_pwm1_chan2_default
&pinctrl_pwm1_chan3_default>;
clock-names = "pwm";
clocks = <&clk_sysin>;
st,pwm-num-chan = <3>;
};
};
};
arch/arm/boot/dts/stih418-b2199.dts
View file @ 0e5e5845
......@@ -86,5 +86,20 @@ mmc0: sdhci@09060000 {
sd-uhs-sdr104;
sd-uhs-ddr50;
};
miphy28lp_phy: miphy28lp@9b22000 {
phy_port0: port@9b22000 {
st,osc-rdy;
};
phy_port1: port@9b2a000 {
st,osc-force-ext;
};
};
st_dwc3: dwc3@8f94000 {
status = "okay";
};
};
};
arch/arm/boot/dts/stihxxx-b2120.dtsi
View file @ 0e5e5845
......@@ -74,5 +74,10 @@ phy_port1: port@9b2a000 {
st,osc-force-ext;
};
};
st_dwc3: dwc3@8f94000 {
status = "okay";
};
};
};
arch/arm/mach-sti/Kconfig
View file @ 0e5e5845
menuconfig ARCH_STI
bool "STMicroelectronics Consumer Electronics SOCs" if ARCH_MULTI_V7
select ARM_GIC
select ST_IRQCHIP
select ARM_GLOBAL_TIMER
select PINCTRL
select PINCTRL_ST
......
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