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Commit 0f47ef3f authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Jernej Skrabec
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arm: dts: allwinner: drop underscore in node names 

Underscores should not be used in node names (dtc with W=2 warns about
them), so replace them with hyphens.  Use also generic name for pwrseq
node, because generic naming is favored by Devicetree spec.  All the
clocks affected by this change use clock-output-names, so resulting
clock name should not change.  Functional impact checked with comparing
before/after DTBs with dtx_diff and fdtdump.
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240317184130.157695-4-krzysztof.kozlowski@linaro.orgSigned-off-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
parent f5217bc4
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Showing with 86 additions and 86 deletions
arch/arm/boot/dts/allwinner/sun5i-a13.dtsi
View file @ 0f47ef3f
......@@ -62,14 +62,14 @@ map0 {
};
trips {
cpu_alert0: cpu_alert0 {
cpu_alert0: cpu-alert0 {
/* milliCelsius */
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu_crit {
cpu_crit: cpu-crit {
/* milliCelsius */
temperature = <100000>;
hysteresis = <2000>;
......
arch/arm/boot/dts/allwinner/sun5i-gr8-chip-pro.dts
View file @ 0f47ef3f
......@@ -77,7 +77,7 @@ led-0 {
};
};
mmc0_pwrseq: mmc0_pwrseq {
mmc0_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */
};
......
arch/arm/boot/dts/allwinner/sun5i-r8-chip.dts
View file @ 0f47ef3f
......@@ -77,7 +77,7 @@ led-0 {
};
};
mmc0_pwrseq: mmc0_pwrseq {
mmc0_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */
};
......
arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts
View file @ 0f47ef3f
......@@ -109,7 +109,7 @@ vga_dac_out: endpoint {
};
};
reg_vga_3v3: vga_3v3_regulator {
reg_vga_3v3: vga-3v3-regulator {
compatible = "regulator-fixed";
regulator-name = "vga-3v3";
regulator-min-microvolt = <3300000>;
......@@ -119,7 +119,7 @@ reg_vga_3v3: vga_3v3_regulator {
gpio = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */
};
......
arch/arm/boot/dts/allwinner/sun6i-a31.dtsi
View file @ 0f47ef3f
......@@ -179,14 +179,14 @@ map0 {
};
trips {
cpu_alert0: cpu_alert0 {
cpu_alert0: cpu-alert0 {
/* milliCelsius */
temperature = <70000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu_crit {
cpu_crit: cpu-crit {
/* milliCelsius */
temperature = <100000>;
hysteresis = <2000>;
......@@ -1318,7 +1318,7 @@ prcm@1f01400 {
compatible = "allwinner,sun6i-a31-prcm";
reg = <0x01f01400 0x200>;
ar100: ar100_clk {
ar100: ar100-clk {
compatible = "allwinner,sun6i-a31-ar100-clk";
#clock-cells = <0>;
clocks = <&rtc CLK_OSC32K>, <&osc24M>,
......@@ -1327,7 +1327,7 @@ ar100: ar100_clk {
clock-output-names = "ar100";
};
ahb0: ahb0_clk {
ahb0: ahb0-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <1>;
......@@ -1336,14 +1336,14 @@ ahb0: ahb0_clk {
clock-output-names = "ahb0";
};
apb0: apb0_clk {
apb0: apb0-clk {
compatible = "allwinner,sun6i-a31-apb0-clk";
#clock-cells = <0>;
clocks = <&ahb0>;
clock-output-names = "apb0";
};
apb0_gates: apb0_gates_clk {
apb0_gates: apb0-gates-clk {
compatible = "allwinner,sun6i-a31-apb0-gates-clk";
#clock-cells = <1>;
clocks = <&apb0>;
......@@ -1353,14 +1353,14 @@ apb0_gates: apb0_gates_clk {
"apb0_i2c";
};
ir_clk: ir_clk {
ir_clk: ir-clk {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
clocks = <&rtc CLK_OSC32K>, <&osc24M>;
clock-output-names = "ir";
};
apb0_rst: apb0_rst {
apb0_rst: apb0-rst {
compatible = "allwinner,sun6i-a31-clock-reset";
#reset-cells = <1>;
};
......
arch/arm/boot/dts/allwinner/sun6i-a31s-sinovoip-bpi-m2.dts
View file @ 0f47ef3f
......@@ -75,7 +75,7 @@ led-2 {
};
};
mmc2_pwrseq: mmc2_pwrseq {
mmc2_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 WIFI_EN */
};
......
arch/arm/boot/dts/allwinner/sun7i-a20-bananapi-m1-plus.dts
View file @ 0f47ef3f
......@@ -86,7 +86,7 @@ led-1 {
};
};
mmc3_pwrseq: mmc3_pwrseq {
mmc3_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */
};
......
arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
View file @ 0f47ef3f
......@@ -96,7 +96,7 @@ led-3 {
};
};
mmc3_pwrseq: mmc3_pwrseq {
mmc3_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */
clocks = <&ccu CLK_OUT_A>;
......
arch/arm/boot/dts/allwinner/sun7i-a20-hummingbird.dts
View file @ 0f47ef3f
......@@ -65,7 +65,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
reg_mmc3_vdd: mmc3_vdd {
reg_mmc3_vdd: regulator-mmc3-vdd {
compatible = "regulator-fixed";
regulator-name = "mmc3_vdd";
regulator-min-microvolt = <3000000>;
......@@ -74,7 +74,7 @@ reg_mmc3_vdd: mmc3_vdd {
gpio = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
};
reg_gmac_vdd: gmac_vdd {
reg_gmac_vdd: regulator-gmac-vdd {
compatible = "regulator-fixed";
regulator-name = "gmac_vdd";
regulator-min-microvolt = <3000000>;
......
arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb-emmc.dts
View file @ 0f47ef3f
......@@ -14,7 +14,7 @@ / {
model = "Olimex A20-Olimex-SOM-EVB-eMMC";
compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20";
mmc2_pwrseq: mmc2_pwrseq {
mmc2_pwrseq: pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&pio 2 18 GPIO_ACTIVE_LOW>;
};
......
arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb-emmc.dts
View file @ 0f47ef3f
......@@ -13,7 +13,7 @@ / {
model = "Olimex A20-SOM204-EVB-eMMC";
compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20";
mmc2_pwrseq: mmc2_pwrseq {
mmc2_pwrseq: pwrseq-1 {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
};
......
arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts
View file @ 0f47ef3f
......@@ -65,7 +65,7 @@ led-2 {
};
};
rtl_pwrseq: rtl_pwrseq {
rtl_pwrseq: pwrseq-0 {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>;
};
......@@ -177,7 +177,7 @@ &mmc3 {
non-removable;
status = "okay";
rtl8723bs: sdio_wifi@1 {
rtl8723bs: wifi@1 {
reg = <1>;
};
};
......
arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts
View file @ 0f47ef3f
......@@ -82,7 +82,7 @@ led {
};
};
reg_axp_ipsout: axp_ipsout {
reg_axp_ipsout: regulator-axp-ipsout {
compatible = "regulator-fixed";
regulator-name = "axp-ipsout";
regulator-min-microvolt = <5000000>;
......
arch/arm/boot/dts/allwinner/sun7i-a20-wits-pro-a20-dkt.dts
View file @ 0f47ef3f
......@@ -60,7 +60,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
mmc3_pwrseq: mmc3_pwrseq {
mmc3_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */
};
......
arch/arm/boot/dts/allwinner/sun7i-a20.dtsi
View file @ 0f47ef3f
......@@ -153,14 +153,14 @@ map0 {
};
trips {
cpu_alert0: cpu_alert0 {
cpu_alert0: cpu-alert0 {
/* milliCelsius */
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu_crit {
cpu_crit: cpu-crit {
/* milliCelsius */
temperature = <100000>;
hysteresis = <2000>;
......
arch/arm/boot/dts/allwinner/sun8i-a23-a33.dtsi
View file @ 0f47ef3f
......@@ -108,7 +108,7 @@ clocks {
#size-cells = <1>;
ranges;
osc24M: osc24M_clk {
osc24M: osc24M-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
......@@ -116,7 +116,7 @@ osc24M: osc24M_clk {
clock-output-names = "osc24M";
};
ext_osc32k: ext_osc32k_clk {
ext_osc32k: ext-osc32k-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
......@@ -733,7 +733,7 @@ prcm@1f01400 {
compatible = "allwinner,sun8i-a23-prcm";
reg = <0x01f01400 0x200>;
ar100: ar100_clk {
ar100: ar100-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <1>;
......@@ -742,7 +742,7 @@ ar100: ar100_clk {
clock-output-names = "ar100";
};
ahb0: ahb0_clk {
ahb0: ahb0-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <1>;
......@@ -751,14 +751,14 @@ ahb0: ahb0_clk {
clock-output-names = "ahb0";
};
apb0: apb0_clk {
apb0: apb0-clk {
compatible = "allwinner,sun8i-a23-apb0-clk";
#clock-cells = <0>;
clocks = <&ahb0>;
clock-output-names = "apb0";
};
apb0_gates: apb0_gates_clk {
apb0_gates: apb0-gates-clk {
compatible = "allwinner,sun8i-a23-apb0-gates-clk";
#clock-cells = <1>;
clocks = <&apb0>;
......@@ -767,7 +767,7 @@ apb0_gates: apb0_gates_clk {
"apb0_i2c";
};
apb0_rst: apb0_rst {
apb0_rst: apb0-rst {
compatible = "allwinner,sun6i-a31-clock-reset";
#reset-cells = <1>;
};
......
arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2407pxe03.dts
View file @ 0f47ef3f
......@@ -52,7 +52,7 @@ aliases {
ethernet0 = &esp8089;
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */
/* The esp8089 needs 200 ms after driving wifi-en high */
......@@ -76,7 +76,7 @@ &mmc1 {
non-removable;
status = "okay";
esp8089: sdio_wifi@1 {
esp8089: wifi@1 {
compatible = "esp,esp8089";
reg = <1>;
esp,crystal-26M-en = <2>;
......
arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2809pxe04.dts
View file @ 0f47ef3f
......@@ -52,7 +52,7 @@ aliases {
ethernet0 = &esp8089;
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */
/* The esp8089 needs 200 ms after driving wifi-en high */
......@@ -69,7 +69,7 @@ &mmc1 {
non-removable;
status = "okay";
esp8089: sdio_wifi@1 {
esp8089: wifi@1 {
compatible = "esp,esp8089";
reg = <1>;
esp,crystal-26M-en = <2>;
......
arch/arm/boot/dts/allwinner/sun8i-a33-ga10h-v1.1.dts
View file @ 0f47ef3f
......@@ -85,7 +85,7 @@ &mmc1 {
non-removable;
status = "okay";
rtl8703as: sdio_wifi@1 {
rtl8703as: wifi@1 {
reg = <1>;
};
};
......
arch/arm/boot/dts/allwinner/sun8i-a33-inet-d978-rev2.dts
View file @ 0f47ef3f
......@@ -78,7 +78,7 @@ &mmc1 {
non-removable;
status = "okay";
rtl8723bs: sdio_wifi@1 {
rtl8723bs: wifi@1 {
reg = <1>;
};
};
......
arch/arm/boot/dts/allwinner/sun8i-a33.dtsi
View file @ 0f47ef3f
......@@ -323,35 +323,35 @@ map3 {
};
trips {
cpu_alert0: cpu_alert0 {
cpu_alert0: cpu-alert0 {
/* milliCelsius */
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
gpu_alert0: gpu_alert0 {
gpu_alert0: gpu-alert0 {
/* milliCelsius */
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_alert1: cpu_alert1 {
cpu_alert1: cpu-alert1 {
/* milliCelsius */
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
gpu_alert1: gpu_alert1 {
gpu_alert1: gpu-alert1 {
/* milliCelsius */
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cpu_crit: cpu_crit {
cpu_crit: cpu-crit {
/* milliCelsius */
temperature = <110000>;
hysteresis = <2000>;
......
arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts
View file @ 0f47ef3f
......@@ -95,7 +95,7 @@ reg_usb1_vbus: reg-usb1-vbus {
gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&ac100_rtc 1>;
clock-names = "ext_clock";
......
arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts
View file @ 0f47ef3f
......@@ -144,7 +144,7 @@ spdif_out: spdif-out {
compatible = "linux,spdif-dit";
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&ac100_rtc 1>;
clock-names = "ext_clock";
......
arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
View file @ 0f47ef3f
......@@ -123,7 +123,7 @@ reg_vmain: reg-vmain {
vin-supply = <&reg_vbat>;
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
......
arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
View file @ 0f47ef3f
......@@ -164,7 +164,7 @@ clocks {
ranges;
/* TODO: PRCM block has a mux for this. */
osc24M: osc24M_clk {
osc24M: osc24M-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
......@@ -177,14 +177,14 @@ osc24M: osc24M_clk {
* It is an internal RC-based oscillator.
* TODO: Its controls are in the PRCM block.
*/
osc16M: osc16M_clk {
osc16M: osc16M-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <16000000>;
clock-output-names = "osc16M";
};
osc16Md512: osc16Md512_clk {
osc16Md512: osc16Md512-clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <512>;
......@@ -1127,7 +1127,7 @@ r_ccu: clock@1f01400 {
#reset-cells = <1>;
};
r_cpucfg@1f01c00 {
cpucfg@1f01c00 {
compatible = "allwinner,sun8i-a83t-r-cpucfg";
reg = <0x1f01c00 0x400>;
};
......
arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts
View file @ 0f47ef3f
......@@ -103,7 +103,7 @@ poweroff {
cpu-supply = <&reg_vcc1v2>;
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc CLK_OSC32K_FANOUT>;
......
arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts
View file @ 0f47ef3f
......@@ -90,7 +90,7 @@ &mmc1 {
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc3v3>;
rtl8189etv: sdio_wifi@1 {
rtl8189etv: wifi@1 {
reg = <1>;
};
};
......
arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
View file @ 0f47ef3f
......@@ -80,7 +80,7 @@ status_led {
};
};
reg_vcc_wifi: reg_vcc_wifi {
reg_vcc_wifi: reg-vcc-wifi {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
......@@ -105,7 +105,7 @@ reg_vdd_cpux: vdd-cpux-regulator {
states = <1100000 0>, <1300000 1>;
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>;
post-power-on-delay-ms = <200>;
......@@ -149,7 +149,7 @@ &mmc1 {
* Explicitly define the sdio device, so that we can add an ethernet
* alias for it (which e.g. makes u-boot set a mac-address).
*/
xr819: sdio_wifi@1 {
xr819: wifi@1 {
reg = <1>;
};
};
......
arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts
View file @ 0f47ef3f
......@@ -122,7 +122,7 @@ spdif_out: spdif-out {
compatible = "linux,spdif-dit";
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc CLK_OSC32K_FANOUT>;
......@@ -185,7 +185,7 @@ &mmc1 {
* Explicitly define the sdio device, so that we can add an ethernet
* alias for it (which e.g. makes u-boot set a mac-address).
*/
sdiowifi: sdio_wifi@1 {
sdiowifi: wifi@1 {
reg = <1>;
};
};
......
arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
View file @ 0f47ef3f
......@@ -87,7 +87,7 @@ reg_vdd_sys: vdd-sys {
vin-supply = <&reg_vcc5v0>;
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc CLK_OSC32K_FANOUT>;
......@@ -119,7 +119,7 @@ &mmc1 {
non-removable;
status = "okay";
sdio_wifi: sdio_wifi@1 {
sdio_wifi: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&pio>;
......
arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts
View file @ 0f47ef3f
......@@ -62,7 +62,7 @@ reg_gmac_3v3: gmac-3v3 {
gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
};
......@@ -132,7 +132,7 @@ &mmc1 {
non-removable;
status = "okay";
sdio_wifi: sdio_wifi@1 {
sdio_wifi: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&pio>;
......
arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts
View file @ 0f47ef3f
......@@ -73,7 +73,7 @@ led-1 {
};
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
};
......
arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-r1.dts
View file @ 0f47ef3f
......@@ -43,7 +43,7 @@ reg_vdd_cpux: gpio-regulator {
<1300000 0x1>;
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc CLK_OSC32K_FANOUT>;
......
arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts
View file @ 0f47ef3f
......@@ -105,7 +105,7 @@ switch-4 {
};
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */
};
......@@ -169,7 +169,7 @@ &mmc1 {
* Explicitly define the sdio device, so that we can add an ethernet
* alias for it (which e.g. makes u-boot set a mac-address).
*/
rtl8189: sdio_wifi@1 {
rtl8189: wifi@1 {
reg = <1>;
};
};
......
arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts
View file @ 0f47ef3f
......@@ -143,7 +143,7 @@ &mmc1 {
* Explicitly define the sdio device, so that we can add an ethernet
* alias for it (which e.g. makes u-boot set a mac-address).
*/
rtl8189ftv: sdio_wifi@1 {
rtl8189ftv: wifi@1 {
reg = <1>;
};
};
......
arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts
View file @ 0f47ef3f
......@@ -63,7 +63,7 @@ &mmc1 {
* Explicitly define the sdio device, so that we can add an ethernet
* alias for it (which e.g. makes u-boot set a mac-address).
*/
rtl8189ftv: sdio_wifi@1 {
rtl8189ftv: wifi@1 {
reg = <1>;
};
};
......
arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts
View file @ 0f47ef3f
......@@ -92,7 +92,7 @@ reg_vcc3v3: vcc3v3 {
regulator-max-microvolt = <3300000>;
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
post-power-on-delay-ms = <200>;
......
arch/arm/boot/dts/allwinner/sun8i-q8-common.dtsi
View file @ 0f47ef3f
......@@ -62,7 +62,7 @@ panel_input: endpoint {
};
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
/*
* Q8 boards use various PL# pins as wifi-en. On other boards
......@@ -94,7 +94,7 @@ &mmc1 {
non-removable;
status = "okay";
sdio_wifi: sdio_wifi@1 {
sdio_wifi: wifi@1 {
reg = <1>;
};
};
......
arch/arm/boot/dts/allwinner/sun8i-r16-bananapi-m2m.dts
View file @ 0f47ef3f
......@@ -88,7 +88,7 @@ reg_vcc5v0: vcc5v0 {
regulator-max-microvolt = <5000000>;
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */
clocks = <&rtc CLK_OSC32K_FANOUT>;
......
arch/arm/boot/dts/allwinner/sun8i-r16-parrot.dts
View file @ 0f47ef3f
......@@ -75,7 +75,7 @@ led-2 {
};
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */
};
......
arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts
View file @ 0f47ef3f
......@@ -100,7 +100,7 @@ reg_vcc5v0: vcc5v0 {
enable-active-high;
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
clocks = <&ccu CLK_OUTA>;
......
arch/arm/boot/dts/allwinner/sun8i-r40-oka40i-c.dts
View file @ 0f47ef3f
......@@ -62,7 +62,7 @@ reg_vcc5v0: vcc5v0 {
regulator-max-microvolt = <5000000>;
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN
clocks = <&ccu CLK_OUTA>;
......
arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts
View file @ 0f47ef3f
......@@ -51,7 +51,7 @@ reg_vcc_wifi: vcc-wifi {
startup-delay-us = <200000>;
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */
post-power-on-delay-ms = <200>;
......
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
View file @ 0f47ef3f
......@@ -98,7 +98,7 @@ clocks {
#size-cells = <1>;
ranges;
osc24M: osc24M_clk {
osc24M: osc24M-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
......@@ -106,7 +106,7 @@ osc24M: osc24M_clk {
clock-output-names = "osc24M";
};
osc32k: osc32k_clk {
osc32k: osc32k-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
......
arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts
View file @ 0f47ef3f
......@@ -94,7 +94,7 @@ reg_vcc5v0: vcc5v0 {
enable-active-high;
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
clocks = <&ccu CLK_OUTA>;
......
arch/arm/boot/dts/allwinner/sun9i-a80.dtsi
View file @ 0f47ef3f
......@@ -196,14 +196,14 @@ osc32k: clk-32k {
* The actual TX clock rate is not controlled by the
* gmac_tx clock.
*/
mii_phy_tx_clk: mii_phy_tx_clk {
mii_phy_tx_clk: mii-phy-tx-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "mii_phy_tx";
};
gmac_int_tx_clk: gmac_int_tx_clk {
gmac_int_tx_clk: gmac-int-tx-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
......
arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus.dtsi
View file @ 0f47ef3f
......@@ -98,7 +98,7 @@ reg_gmac_3v3: gmac-3v3 {
gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc CLK_OSC32K_FANOUT>;
......
arch/arm/boot/dts/allwinner/sunxi-h3-h5-emlid-neutis.dtsi
View file @ 0f47ef3f
......@@ -18,7 +18,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */
post-power-on-delay-ms = <200>;
......
arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
View file @ 0f47ef3f
......@@ -83,7 +83,7 @@ clocks {
#size-cells = <1>;
ranges;
osc24M: osc24M_clk {
osc24M: osc24M-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
......@@ -91,7 +91,7 @@ osc24M: osc24M_clk {
clock-output-names = "osc24M";
};
osc32k: osc32k_clk {
osc32k: osc32k-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
......
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