Commit 0f704e12 authored by Phil Edworthy's avatar Phil Edworthy Committed by Simon Horman

ARM: shmobile: r8a7779: Add PCIe clocks

Signed-off-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 9051e912
...@@ -112,7 +112,7 @@ static struct clk *main_clks[] = { ...@@ -112,7 +112,7 @@ static struct clk *main_clks[] = {
}; };
enum { MSTP323, MSTP322, MSTP321, MSTP320, enum { MSTP323, MSTP322, MSTP321, MSTP320,
MSTP115, MSTP114, MSTP116, MSTP115, MSTP114,
MSTP103, MSTP101, MSTP100, MSTP103, MSTP101, MSTP100,
MSTP030, MSTP030,
MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
...@@ -125,6 +125,7 @@ static struct clk mstp_clks[MSTP_NR] = { ...@@ -125,6 +125,7 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */ [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
[MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */ [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
[MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */ [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
[MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */
[MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */ [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
[MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */ [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */
[MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */ [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */
...@@ -161,6 +162,7 @@ static struct clk_lookup lookups[] = { ...@@ -161,6 +162,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("peripheral_clk", &clkp_clk), CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
/* MSTP32 clocks */ /* MSTP32 clocks */
CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */
CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */ CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
......
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