Commit 1005bccd authored by Alex Porosanu's avatar Alex Porosanu Committed by Herbert Xu

crypto: caam - enable instantiation of all RNG4 state handles

RNG4 block contains multiple (i.e. 2) state handles that can be
initialized. This patch adds the necessary code for detecting
which of the two state handles has been instantiated by another
piece of software e.g. u-boot and instantiate the other one (or
both if none was instantiated). Only the state handle(s)
instantiated by this driver will be deinstantiated when removing
the module.
Signed-off-by: default avatarAlex Porosanu <alexandru.porosanu@freescale.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent f1157a5b
This diff is collapsed.
...@@ -87,11 +87,11 @@ struct caam_drv_private { ...@@ -87,11 +87,11 @@ struct caam_drv_private {
/* list of registered hash algorithms (mk generic context handle?) */ /* list of registered hash algorithms (mk generic context handle?) */
struct list_head hash_list; struct list_head hash_list;
#define RNG4_MAX_HANDLES 2
/* RNG4 block */ /* RNG4 block */
bool rng4_init; /* If RNG4 block is initialized by this driver, u32 rng4_sh_init; /* This bitmap shows which of the State
then this will be set; if it was initialized Handles of the RNG4 block are initialized
by another entity (e.g. u-boot), it will be by this driver */
cleared. */
/* /*
* debugfs entries for developer view into driver/device * debugfs entries for developer view into driver/device
......
...@@ -245,7 +245,7 @@ struct rngtst { ...@@ -245,7 +245,7 @@ struct rngtst {
/* RNG4 TRNG test registers */ /* RNG4 TRNG test registers */
struct rng4tst { struct rng4tst {
#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
u32 rtmctl; /* misc. control register */ u32 rtmctl; /* misc. control register */
u32 rtscmisc; /* statistical check misc. register */ u32 rtscmisc; /* statistical check misc. register */
u32 rtpkrrng; /* poker range register */ u32 rtpkrrng; /* poker range register */
...@@ -268,7 +268,11 @@ struct rng4tst { ...@@ -268,7 +268,11 @@ struct rng4tst {
u32 rtfrqcnt; /* PRGM=0: freq. count register */ u32 rtfrqcnt; /* PRGM=0: freq. count register */
}; };
u32 rsvd1[40]; u32 rsvd1[40];
#define RDSTA_SKVT 0x80000000
#define RDSTA_SKVN 0x40000000
#define RDSTA_IF0 0x00000001 #define RDSTA_IF0 0x00000001
#define RDSTA_IF1 0x00000002
#define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0)
u32 rdsta; u32 rdsta;
u32 rsvd2[15]; u32 rsvd2[15];
}; };
...@@ -694,6 +698,7 @@ struct caam_deco { ...@@ -694,6 +698,7 @@ struct caam_deco {
u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */ u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
u32 jr_ctl_lo; u32 jr_ctl_lo;
u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */ u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */
#define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF
u32 op_status_hi; /* DxOPSTA - DECO Operation Status */ u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
u32 op_status_lo; u32 op_status_lo;
u32 rsvd24[2]; u32 rsvd24[2];
......
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