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Commit 109c2f2f authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/gr: switch to subdev printk macros 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent e5c5e4f5
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Inline Side-by-side
Showing with 339 additions and 302 deletions
drivers/gpu/drm/nouveau/include/nvkm/core/enum.h
View file @ 109c2f2f
......@@ -17,6 +17,5 @@ struct nvkm_bitfield {
const char *name;
};
void nvkm_bitfield_print(const struct nvkm_bitfield *, u32 value);
void nvkm_snprintbf(char *, int, const struct nvkm_bitfield *, u32 value);
#endif
drivers/gpu/drm/nouveau/nvkm/core/enum.c
View file @ 109c2f2f
......@@ -49,22 +49,6 @@ nvkm_enum_print(const struct nvkm_enum *en, u32 value)
return en;
}
void
nvkm_bitfield_print(const struct nvkm_bitfield *bf, u32 value)
{
while (bf->name) {
if (value & bf->mask) {
pr_cont(" %s", bf->name);
value &= ~bf->mask;
}
bf++;
}
if (value)
pr_cont(" (unknown bits 0x%08x)", value);
}
void
nvkm_snprintbf(char *data, int size, const struct nvkm_bitfield *bf, u32 value)
{
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
View file @ 109c2f2f
......@@ -1271,7 +1271,8 @@ int
gf100_grctx_generate(struct gf100_gr *gr)
{
struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_bar *bar = device->bar;
struct nvkm_gpuobj *chan;
struct gf100_grctx info;
......@@ -1283,7 +1284,7 @@ gf100_grctx_generate(struct gf100_gr *gr)
ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x80000 + gr->size,
0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan);
if (ret) {
nv_error(gr, "failed to allocate channel memory, %d\n", ret);
nvkm_error(subdev, "failed to allocate chan memory, %d\n", ret);
return ret;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
View file @ 109c2f2f
......@@ -220,13 +220,14 @@ gk20a_gr_dtor(struct nvkm_object *object)
static int
gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
if (nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x40910c) & 0x00000006))
break;
) < 0) {
nv_error(gr, "FECS mem scrubbing timeout\n");
nvkm_error(subdev, "FECS mem scrubbing timeout\n");
return -ETIMEDOUT;
}
......@@ -234,7 +235,7 @@ gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr)
if (!(nvkm_rd32(device, 0x41a10c) & 0x00000006))
break;
) < 0) {
nv_error(gr, "GPCCS mem scrubbing timeout\n");
nvkm_error(subdev, "GPCCS mem scrubbing timeout\n");
return -ETIMEDOUT;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
View file @ 109c2f2f
......@@ -1200,7 +1200,8 @@ bool
nv04_gr_idle(void *obj)
{
struct nvkm_gr *gr = nvkm_gr(obj);
struct nvkm_device *device = gr->engine.subdev.device;
struct nvkm_subdev *subdev = &gr->engine.subdev;
struct nvkm_device *device = subdev->device;
u32 mask = 0xffffffff;
if (nv_device(obj)->card_type == NV_40)
......@@ -1210,8 +1211,8 @@ nv04_gr_idle(void *obj)
if (!(nvkm_rd32(device, NV04_PGRAPH_STATUS) & mask))
break;
) < 0) {
nv_error(gr, "idle timed out with status 0x%08x\n",
nvkm_rd32(device, NV04_PGRAPH_STATUS));
nvkm_error(subdev, "idle timed out with status %08x\n",
nvkm_rd32(device, NV04_PGRAPH_STATUS));
return false;
}
......@@ -1276,6 +1277,7 @@ nv04_gr_intr(struct nvkm_subdev *subdev)
u32 class = nvkm_rd32(device, 0x400180 + subc * 4) & 0xff;
u32 inst = (nvkm_rd32(device, 0x40016c) & 0xffff) << 4;
u32 show = stat;
char msg[128], src[128], sta[128];
unsigned long flags;
spin_lock_irqsave(&gr->lock, flags);
......@@ -1303,17 +1305,14 @@ nv04_gr_intr(struct nvkm_subdev *subdev)
nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
nv_error(gr, "%s", "");
nvkm_bitfield_print(nv04_gr_intr_name, show);
pr_cont(" nsource:");
nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
nvkm_bitfield_print(nv04_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(gr,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, nvkm_client_name(chan), subc, class, mthd,
data);
nvkm_snprintbf(msg, sizeof(msg), nv04_gr_intr_name, show);
nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
nvkm_snprintbf(sta, sizeof(sta), nv04_gr_nstatus, nstatus);
nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
"nstatus %08x [%s] ch %d [%s] subc %d "
"class %04x mthd %04x data %08x\n",
show, msg, nsource, src, nstatus, sta, chid,
nvkm_client_name(chan), subc, class, mthd, data);
}
nvkm_namedb_put(handle);
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
View file @ 109c2f2f
......@@ -690,6 +690,7 @@ static void
nv10_gr_create_pipe(struct nv10_gr_chan *chan)
{
struct nv10_gr *gr = nv10_gr(chan);
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct pipe_state *pipe_state = &chan->pipe_state;
u32 *pipe_state_addr;
int i;
......@@ -702,7 +703,7 @@ nv10_gr_create_pipe(struct nv10_gr_chan *chan)
u32 *__end_addr = pipe_state->pipe_##addr + \
ARRAY_SIZE(pipe_state->pipe_##addr); \
if (pipe_state_addr != __end_addr) \
nv_error(gr, "incomplete pipe init for 0x%x : %p/%p\n", \
nvkm_error(subdev, "incomplete pipe init for 0x%x : %p/%p\n", \
addr, pipe_state_addr, __end_addr); \
} while (0)
#define NV_WRITE_PIPE_INIT(value) *(pipe_state_addr++) = value
......@@ -844,24 +845,26 @@ nv10_gr_create_pipe(struct nv10_gr_chan *chan)
static int
nv10_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
int i;
for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) {
if (nv10_gr_ctx_regs[i] == reg)
return i;
}
nv_error(gr, "unknow offset nv10_ctx_regs %d\n", reg);
nvkm_error(subdev, "unknow offset nv10_ctx_regs %d\n", reg);
return -1;
}
static int
nv17_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
int i;
for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) {
if (nv17_gr_ctx_regs[i] == reg)
return i;
}
nv_error(gr, "unknow offset nv17_ctx_regs %d\n", reg);
nvkm_error(subdev, "unknow offset nv17_ctx_regs %d\n", reg);
return -1;
}
......@@ -1177,6 +1180,7 @@ nv10_gr_intr(struct nvkm_subdev *subdev)
u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
u32 show = stat;
char msg[128], src[128], sta[128];
unsigned long flags;
spin_lock_irqsave(&gr->lock, flags);
......@@ -1204,17 +1208,14 @@ nv10_gr_intr(struct nvkm_subdev *subdev)
nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
nv_error(gr, "%s", "");
nvkm_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(gr,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, nvkm_client_name(chan), subc, class, mthd,
data);
nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
"nstatus %08x [%s] ch %d [%s] subc %d "
"class %04x mthd %04x data %08x\n",
show, msg, nsource, src, nstatus, sta, chid,
nvkm_client_name(chan), subc, class, mthd, data);
}
nvkm_namedb_put(handle);
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
View file @ 109c2f2f
......@@ -207,6 +207,7 @@ nv20_gr_intr(struct nvkm_subdev *subdev)
u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
u32 show = stat;
char msg[128], src[128], sta[128];
engctx = nvkm_engctx_get(engine, chid);
if (stat & NV_PGRAPH_INTR_ERROR) {
......@@ -222,17 +223,14 @@ nv20_gr_intr(struct nvkm_subdev *subdev)
nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
nv_error(gr, "%s", "");
nvkm_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(gr,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, nvkm_client_name(engctx), subc, class, mthd,
data);
nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
"nstatus %08x [%s] ch %d [%s] subc %d "
"class %04x mthd %04x data %08x\n",
show, msg, nsource, src, nstatus, sta, chid,
nvkm_client_name(engctx), subc, class, mthd, data);
}
nvkm_engctx_put(engctx);
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
View file @ 109c2f2f
......@@ -155,7 +155,8 @@ nv40_gr_context_fini(struct nvkm_object *object, bool suspend)
{
struct nv40_gr *gr = (void *)object->engine;
struct nv40_gr_chan *chan = (void *)object;
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4;
int ret = 0;
......@@ -172,7 +173,7 @@ nv40_gr_context_fini(struct nvkm_object *object, bool suspend)
break;
) < 0) {
u32 insn = nvkm_rd32(device, 0x400308);
nv_warn(gr, "ctxprog timeout 0x%08x\n", insn);
nvkm_warn(subdev, "ctxprog timeout %08x\n", insn);
ret = -EBUSY;
}
}
......@@ -302,6 +303,7 @@ nv40_gr_intr(struct nvkm_subdev *subdev)
u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xffff;
u32 show = stat;
char msg[128], src[128], sta[128];
int chid;
engctx = nvkm_engctx_get(engine, inst);
......@@ -324,17 +326,15 @@ nv40_gr_intr(struct nvkm_subdev *subdev)
nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
nv_error(gr, "%s", "");
nvkm_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(gr,
"ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, inst << 4, nvkm_client_name(engctx), subc,
class, mthd, data);
nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
"nstatus %08x [%s] ch %d [%08x %s] subc %d "
"class %04x mthd %04x data %08x\n",
show, msg, nsource, src, nstatus, sta, chid,
inst << 4, nvkm_client_name(engctx), subc,
class, mthd, data);
}
nvkm_engctx_put(engctx);
......
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