Commit 11b28341 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Mika Kuoppala

drm/i915/gen9: Enable must set chicken bits in config0 reg

The bspec states that these must be set in CONFIG0 for all gen9.

v2: rebase
v3: fix spacing (Matthew)

References: HSD#2134995
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-13-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit b033bb6d)
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
parent 738fa1b3
...@@ -220,6 +220,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) ...@@ -220,6 +220,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define ECOCHK_PPGTT_WT_HSW (0x2<<3) #define ECOCHK_PPGTT_WT_HSW (0x2<<3)
#define ECOCHK_PPGTT_WB_HSW (0x3<<3) #define ECOCHK_PPGTT_WB_HSW (0x3<<3)
#define GEN8_CONFIG0 _MMIO(0xD00)
#define GEN9_DEFAULT_FIXES (1 << 3 | 1 << 2 | 1 << 1)
#define GAC_ECO_BITS _MMIO(0x14090) #define GAC_ECO_BITS _MMIO(0x14090)
#define ECOBITS_SNB_BIT (1<<13) #define ECOBITS_SNB_BIT (1<<13)
#define ECOBITS_PPGTT_CACHE64B (3<<8) #define ECOBITS_PPGTT_CACHE64B (3<<8)
......
...@@ -54,14 +54,24 @@ ...@@ -54,14 +54,24 @@
#define INTEL_RC6p_ENABLE (1<<1) #define INTEL_RC6p_ENABLE (1<<1)
#define INTEL_RC6pp_ENABLE (1<<2) #define INTEL_RC6pp_ENABLE (1<<2)
static void bxt_init_clock_gating(struct drm_device *dev) static void gen9_init_clock_gating(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
/* See Bspec note for PSR2_CTL bit 31, Wa#828:bxt */ /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
I915_WRITE(CHICKEN_PAR1_1, I915_WRITE(CHICKEN_PAR1_1,
I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
I915_WRITE(GEN8_CONFIG0,
I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
}
static void bxt_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
gen9_init_clock_gating(dev);
/* WaDisableSDEUnitClockGating:bxt */ /* WaDisableSDEUnitClockGating:bxt */
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
GEN8_SDEUNIT_CLOCK_GATE_DISABLE); GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
...@@ -6706,9 +6716,7 @@ static void kabylake_init_clock_gating(struct drm_device *dev) ...@@ -6706,9 +6716,7 @@ static void kabylake_init_clock_gating(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
/* See Bspec note for PSR2_CTL bit 31, Wa#828:kbl */ gen9_init_clock_gating(dev);
I915_WRITE(CHICKEN_PAR1_1,
I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
/* WaDisableSDEUnitClockGating:kbl */ /* WaDisableSDEUnitClockGating:kbl */
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
...@@ -6718,11 +6726,7 @@ static void kabylake_init_clock_gating(struct drm_device *dev) ...@@ -6718,11 +6726,7 @@ static void kabylake_init_clock_gating(struct drm_device *dev)
static void skylake_init_clock_gating(struct drm_device *dev) static void skylake_init_clock_gating(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; gen9_init_clock_gating(dev);
/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl */
I915_WRITE(CHICKEN_PAR1_1,
I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
} }
static void broadwell_init_clock_gating(struct drm_device *dev) static void broadwell_init_clock_gating(struct drm_device *dev)
......
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