Commit 1218a2e3 authored by Leo Liu's avatar Leo Liu Committed by Alex Deucher

drm/amdgpu: make software ring functions reuseable for newer VCN

Software ring will be supported only from VCN4
Signed-off-by: default avatarLeo Liu <leo.liu@amd.com>
Reviewed-by: default avatarJames Zhu <James.Zhu@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ed1db32e
...@@ -1728,8 +1728,8 @@ static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) ...@@ -1728,8 +1728,8 @@ static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
} }
} }
static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
u64 seq, uint32_t flags) u64 seq, uint32_t flags)
{ {
WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
...@@ -1740,15 +1740,13 @@ static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, ...@@ -1740,15 +1740,13 @@ static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP); amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP);
} }
static void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring) void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring)
{ {
amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
} }
static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
struct amdgpu_job *job, struct amdgpu_ib *ib, uint32_t flags)
struct amdgpu_ib *ib,
uint32_t flags)
{ {
uint32_t vmid = AMDGPU_JOB_GET_VMID(job); uint32_t vmid = AMDGPU_JOB_GET_VMID(job);
...@@ -1759,8 +1757,8 @@ static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, ...@@ -1759,8 +1757,8 @@ static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, ib->length_dw); amdgpu_ring_write(ring, ib->length_dw);
} }
static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
uint32_t val, uint32_t mask) uint32_t val, uint32_t mask)
{ {
amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT); amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT);
amdgpu_ring_write(ring, reg << 2); amdgpu_ring_write(ring, reg << 2);
...@@ -1768,8 +1766,8 @@ static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_ ...@@ -1768,8 +1766,8 @@ static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_
amdgpu_ring_write(ring, val); amdgpu_ring_write(ring, val);
} }
static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring, void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
uint32_t vmid, uint64_t pd_addr) uint32_t vmid, uint64_t pd_addr)
{ {
struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
uint32_t data0, data1, mask; uint32_t data0, data1, mask;
...@@ -1783,7 +1781,8 @@ static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring, ...@@ -1783,7 +1781,8 @@ static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask); vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask);
} }
static void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
uint32_t val)
{ {
amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE); amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE);
amdgpu_ring_write(ring, reg << 2); amdgpu_ring_write(ring, reg << 2);
......
...@@ -26,4 +26,16 @@ ...@@ -26,4 +26,16 @@
extern const struct amdgpu_ip_block_version vcn_v3_0_ip_block; extern const struct amdgpu_ip_block_version vcn_v3_0_ip_block;
void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
u64 seq, uint32_t flags);
void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring);
void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
struct amdgpu_ib *ib, uint32_t flags);
void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
uint32_t val, uint32_t mask);
void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
uint32_t vmid, uint64_t pd_addr);
void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
uint32_t val);
#endif /* __VCN_V3_0_H__ */ #endif /* __VCN_V3_0_H__ */
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