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Commit 13079a73 authored by Jean-Christophe PLAGNIOL-VILLARD's avatar Jean-Christophe PLAGNIOL-VILLARD
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ARM: at91: make DBGU soc independent 

we will select now the DBGU used by the soc at Kconfig level

For the DEBUG_LL and early_printk this will allow to select which DBGU to use
this will also allow to select them when multiple SOC are enabled
Signed-off-by: default avatarJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
parent c1c30a29
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Inline Side-by-side
Showing with 72 additions and 33 deletions
arch/arm/Kconfig.debug
View file @ 13079a73
...@@ -100,6 +100,14 @@ choice ...@@ -100,6 +100,14 @@ choice
Note that the system will appear to hang during boot if there Note that the system will appear to hang during boot if there
is nothing connected to read from the DCC. is nothing connected to read from the DCC.
config AT91_DEBUG_LL_DBGU0
bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl"
depends on HAVE_AT91_DBGU0
config AT91_DEBUG_LL_DBGU1
bool "Kernel low-level debugging on 9263, 9g45 and cap9"
depends on HAVE_AT91_DBGU1
config DEBUG_FOOTBRIDGE_COM1 config DEBUG_FOOTBRIDGE_COM1
bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1" bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
depends on FOOTBRIDGE depends on FOOTBRIDGE
......
arch/arm/mach-at91/Kconfig
View file @ 13079a73
...@@ -3,6 +3,12 @@ if ARCH_AT91 ...@@ -3,6 +3,12 @@ if ARCH_AT91
config HAVE_AT91_DATAFLASH_CARD config HAVE_AT91_DATAFLASH_CARD
bool bool
config HAVE_AT91_DBGU0
bool
config HAVE_AT91_DBGU1
bool
config HAVE_AT91_USART3 config HAVE_AT91_USART3
bool bool
...@@ -21,12 +27,14 @@ config ARCH_AT91RM9200 ...@@ -21,12 +27,14 @@ config ARCH_AT91RM9200
bool "AT91RM9200" bool "AT91RM9200"
select CPU_ARM920T select CPU_ARM920T
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select HAVE_AT91_DBGU0
select HAVE_AT91_USART3 select HAVE_AT91_USART3
config ARCH_AT91SAM9260 config ARCH_AT91SAM9260
bool "AT91SAM9260 or AT91SAM9XE" bool "AT91SAM9260 or AT91SAM9XE"
select CPU_ARM926T select CPU_ARM926T
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select HAVE_AT91_DBGU0
select HAVE_AT91_USART3 select HAVE_AT91_USART3
select HAVE_AT91_USART4 select HAVE_AT91_USART4
select HAVE_AT91_USART5 select HAVE_AT91_USART5
...@@ -37,11 +45,13 @@ config ARCH_AT91SAM9261 ...@@ -37,11 +45,13 @@ config ARCH_AT91SAM9261
select CPU_ARM926T select CPU_ARM926T
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select HAVE_FB_ATMEL select HAVE_FB_ATMEL
select HAVE_AT91_DBGU0
config ARCH_AT91SAM9G10 config ARCH_AT91SAM9G10
bool "AT91SAM9G10" bool "AT91SAM9G10"
select CPU_ARM926T select CPU_ARM926T
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL select HAVE_FB_ATMEL
config ARCH_AT91SAM9263 config ARCH_AT91SAM9263
...@@ -50,6 +60,7 @@ config ARCH_AT91SAM9263 ...@@ -50,6 +60,7 @@ config ARCH_AT91SAM9263
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select HAVE_FB_ATMEL select HAVE_FB_ATMEL
select HAVE_NET_MACB select HAVE_NET_MACB
select HAVE_AT91_DBGU1
config ARCH_AT91SAM9RL config ARCH_AT91SAM9RL
bool "AT91SAM9RL" bool "AT91SAM9RL"
...@@ -57,11 +68,13 @@ config ARCH_AT91SAM9RL ...@@ -57,11 +68,13 @@ config ARCH_AT91SAM9RL
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select HAVE_AT91_USART3 select HAVE_AT91_USART3
select HAVE_FB_ATMEL select HAVE_FB_ATMEL
select HAVE_AT91_DBGU0
config ARCH_AT91SAM9G20 config ARCH_AT91SAM9G20
bool "AT91SAM9G20" bool "AT91SAM9G20"
select CPU_ARM926T select CPU_ARM926T
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select HAVE_AT91_DBGU0
select HAVE_AT91_USART3 select HAVE_AT91_USART3
select HAVE_AT91_USART4 select HAVE_AT91_USART4
select HAVE_AT91_USART5 select HAVE_AT91_USART5
...@@ -74,6 +87,7 @@ config ARCH_AT91SAM9G45 ...@@ -74,6 +87,7 @@ config ARCH_AT91SAM9G45
select HAVE_AT91_USART3 select HAVE_AT91_USART3
select HAVE_FB_ATMEL select HAVE_FB_ATMEL
select HAVE_NET_MACB select HAVE_NET_MACB
select HAVE_AT91_DBGU1
config ARCH_AT91CAP9 config ARCH_AT91CAP9
bool "AT91CAP9" bool "AT91CAP9"
...@@ -81,6 +95,7 @@ config ARCH_AT91CAP9 ...@@ -81,6 +95,7 @@ config ARCH_AT91CAP9
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select HAVE_FB_ATMEL select HAVE_FB_ATMEL
select HAVE_NET_MACB select HAVE_NET_MACB
select HAVE_AT91_DBGU1
config ARCH_AT91X40 config ARCH_AT91X40
bool "AT91x40" bool "AT91x40"
...@@ -510,8 +525,13 @@ config AT91_TIMER_HZ ...@@ -510,8 +525,13 @@ config AT91_TIMER_HZ
choice choice
prompt "Select a UART for early kernel messages" prompt "Select a UART for early kernel messages"
config AT91_EARLY_DBGU config AT91_EARLY_DBGU0
bool "DBGU" bool "DBGU on rm9200, 9260/9g20, 9261/9g10 and 9rl"
depends on HAVE_AT91_DBGU0
config AT91_EARLY_DBGU1
bool "DBGU on 9263, 9g45 and cap9"
depends on HAVE_AT91_DBGU1
config AT91_EARLY_USART0 config AT91_EARLY_USART0
bool "USART0" bool "USART0"
......
arch/arm/mach-at91/at91cap9_devices.c
View file @ 13079a73
...@@ -1030,8 +1030,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {} ...@@ -1030,8 +1030,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
#if defined(CONFIG_SERIAL_ATMEL) #if defined(CONFIG_SERIAL_ATMEL)
static struct resource dbgu_resources[] = { static struct resource dbgu_resources[] = {
[0] = { [0] = {
.start = AT91_BASE_SYS + AT91_DBGU, .start = AT91CAP9_BASE_DBGU,
.end = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1, .end = AT91CAP9_BASE_DBGU + SZ_512 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
......
arch/arm/mach-at91/at91rm9200_devices.c
View file @ 13079a73
...@@ -877,8 +877,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {} ...@@ -877,8 +877,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
#if defined(CONFIG_SERIAL_ATMEL) #if defined(CONFIG_SERIAL_ATMEL)
static struct resource dbgu_resources[] = { static struct resource dbgu_resources[] = {
[0] = { [0] = {
.start = AT91_BASE_SYS + AT91_DBGU, .start = AT91RM9200_BASE_DBGU,
.end = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1, .end = AT91RM9200_BASE_DBGU + SZ_512 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
......
arch/arm/mach-at91/at91sam9260_devices.c
View file @ 13079a73
...@@ -846,8 +846,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {} ...@@ -846,8 +846,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
#if defined(CONFIG_SERIAL_ATMEL) #if defined(CONFIG_SERIAL_ATMEL)
static struct resource dbgu_resources[] = { static struct resource dbgu_resources[] = {
[0] = { [0] = {
.start = AT91_BASE_SYS + AT91_DBGU, .start = AT91SAM9260_BASE_DBGU,
.end = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1, .end = AT91SAM9260_BASE_DBGU + SZ_512 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
......
arch/arm/mach-at91/at91sam9261_devices.c
View file @ 13079a73
...@@ -825,8 +825,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {} ...@@ -825,8 +825,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
#if defined(CONFIG_SERIAL_ATMEL) #if defined(CONFIG_SERIAL_ATMEL)
static struct resource dbgu_resources[] = { static struct resource dbgu_resources[] = {
[0] = { [0] = {
.start = AT91_BASE_SYS + AT91_DBGU, .start = AT91SAM9261_BASE_DBGU,
.end = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1, .end = AT91SAM9261_BASE_DBGU + SZ_512 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
......
arch/arm/mach-at91/at91sam9263_devices.c
View file @ 13079a73
...@@ -1205,8 +1205,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {} ...@@ -1205,8 +1205,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
static struct resource dbgu_resources[] = { static struct resource dbgu_resources[] = {
[0] = { [0] = {
.start = AT91_BASE_SYS + AT91_DBGU, .start = AT91SAM9263_BASE_DBGU,
.end = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1, .end = AT91SAM9263_BASE_DBGU + SZ_512 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
......
arch/arm/mach-at91/at91sam9g45_devices.c
View file @ 13079a73
...@@ -1341,8 +1341,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {} ...@@ -1341,8 +1341,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
#if defined(CONFIG_SERIAL_ATMEL) #if defined(CONFIG_SERIAL_ATMEL)
static struct resource dbgu_resources[] = { static struct resource dbgu_resources[] = {
[0] = { [0] = {
.start = AT91_BASE_SYS + AT91_DBGU, .start = AT91SAM9G45_BASE_DBGU,
.end = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1, .end = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
......
arch/arm/mach-at91/at91sam9rl_devices.c
View file @ 13079a73
...@@ -917,8 +917,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {} ...@@ -917,8 +917,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
#if defined(CONFIG_SERIAL_ATMEL) #if defined(CONFIG_SERIAL_ATMEL)
static struct resource dbgu_resources[] = { static struct resource dbgu_resources[] = {
[0] = { [0] = {
.start = AT91_BASE_SYS + AT91_DBGU, .start = AT91SAM9RL_BASE_DBGU,
.end = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1, .end = AT91SAM9RL_BASE_DBGU + SZ_512 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
......
arch/arm/mach-at91/include/mach/at91_dbgu.h
View file @ 13079a73
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
#define dbgu_readl(dbgu, field) \ #define dbgu_readl(dbgu, field) \
__raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field) __raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field)
#ifdef AT91_DBGU #if !defined(CONFIG_ARCH_AT91X40)
#define AT91_DBGU_CR (0x00) /* Control Register */ #define AT91_DBGU_CR (0x00) /* Control Register */
#define AT91_DBGU_MR (0x04) /* Mode Register */ #define AT91_DBGU_MR (0x04) /* Mode Register */
#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */ #define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
......
arch/arm/mach-at91/include/mach/at91cap9.h
View file @ 13079a73
...@@ -82,7 +82,6 @@ ...@@ -82,7 +82,6 @@
#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) #define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
...@@ -93,6 +92,7 @@ ...@@ -93,6 +92,7 @@
#define AT91CAP9_BASE_ECC 0xffffe200 #define AT91CAP9_BASE_ECC 0xffffe200
#define AT91CAP9_BASE_DMA 0xffffec00 #define AT91CAP9_BASE_DMA 0xffffec00
#define AT91CAP9_BASE_SMC 0xffffe800 #define AT91CAP9_BASE_SMC 0xffffe800
#define AT91CAP9_BASE_DBGU AT91_BASE_DBGU1
#define AT91CAP9_BASE_PIOA 0xfffff200 #define AT91CAP9_BASE_PIOA 0xfffff200
#define AT91CAP9_BASE_PIOB 0xfffff400 #define AT91CAP9_BASE_PIOB 0xfffff400
#define AT91CAP9_BASE_PIOC 0xfffff600 #define AT91CAP9_BASE_PIOC 0xfffff600
......
arch/arm/mach-at91/include/mach/at91rm9200.h
View file @ 13079a73
...@@ -80,12 +80,12 @@ ...@@ -80,12 +80,12 @@
* System Peripherals (offset from AT91_BASE_SYS) * System Peripherals (offset from AT91_BASE_SYS)
*/ */
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */ #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */ #define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */ #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ #define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */ #define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */ #define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */ #define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
......
arch/arm/mach-at91/include/mach/at91sam9260.h
View file @ 13079a73
...@@ -83,13 +83,13 @@ ...@@ -83,13 +83,13 @@
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91SAM9260_BASE_ECC 0xffffe800 #define AT91SAM9260_BASE_ECC 0xffffe800
#define AT91SAM9260_BASE_SMC 0xffffec00 #define AT91SAM9260_BASE_SMC 0xffffec00
#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
#define AT91SAM9260_BASE_PIOA 0xfffff400 #define AT91SAM9260_BASE_PIOA 0xfffff400
#define AT91SAM9260_BASE_PIOB 0xfffff600 #define AT91SAM9260_BASE_PIOB 0xfffff600
#define AT91SAM9260_BASE_PIOC 0xfffff800 #define AT91SAM9260_BASE_PIOC 0xfffff800
......
arch/arm/mach-at91/include/mach/at91sam9261.h
View file @ 13079a73
...@@ -68,12 +68,12 @@ ...@@ -68,12 +68,12 @@
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91SAM9261_BASE_SMC 0xffffec00 #define AT91SAM9261_BASE_SMC 0xffffec00
#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0
#define AT91SAM9261_BASE_PIOA 0xfffff400 #define AT91SAM9261_BASE_PIOA 0xfffff400
#define AT91SAM9261_BASE_PIOB 0xfffff600 #define AT91SAM9261_BASE_PIOB 0xfffff600
#define AT91SAM9261_BASE_PIOC 0xfffff800 #define AT91SAM9261_BASE_PIOC 0xfffff800
......
arch/arm/mach-at91/include/mach/at91sam9263.h
View file @ 13079a73
...@@ -77,7 +77,6 @@ ...@@ -77,7 +77,6 @@
#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) #define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
...@@ -87,6 +86,7 @@ ...@@ -87,6 +86,7 @@
#define AT91SAM9263_BASE_SMC0 0xffffe400 #define AT91SAM9263_BASE_SMC0 0xffffe400
#define AT91SAM9263_BASE_ECC1 0xffffe600 #define AT91SAM9263_BASE_ECC1 0xffffe600
#define AT91SAM9263_BASE_SMC1 0xffffea00 #define AT91SAM9263_BASE_SMC1 0xffffea00
#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1
#define AT91SAM9263_BASE_PIOA 0xfffff200 #define AT91SAM9263_BASE_PIOA 0xfffff200
#define AT91SAM9263_BASE_PIOB 0xfffff400 #define AT91SAM9263_BASE_PIOB 0xfffff400
#define AT91SAM9263_BASE_PIOC 0xfffff600 #define AT91SAM9263_BASE_PIOC 0xfffff600
......
arch/arm/mach-at91/include/mach/at91sam9g45.h
View file @ 13079a73
...@@ -89,7 +89,6 @@ ...@@ -89,7 +89,6 @@
#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) #define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
...@@ -99,6 +98,7 @@ ...@@ -99,6 +98,7 @@
#define AT91SAM9G45_BASE_ECC 0xffffe200 #define AT91SAM9G45_BASE_ECC 0xffffe200
#define AT91SAM9G45_BASE_DMA 0xffffec00 #define AT91SAM9G45_BASE_DMA 0xffffec00
#define AT91SAM9G45_BASE_SMC 0xffffe800 #define AT91SAM9G45_BASE_SMC 0xffffe800
#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1
#define AT91SAM9G45_BASE_PIOA 0xfffff200 #define AT91SAM9G45_BASE_PIOA 0xfffff200
#define AT91SAM9G45_BASE_PIOB 0xfffff400 #define AT91SAM9G45_BASE_PIOB 0xfffff400
#define AT91SAM9G45_BASE_PIOC 0xfffff600 #define AT91SAM9G45_BASE_PIOC 0xfffff600
......
arch/arm/mach-at91/include/mach/at91sam9rl.h
View file @ 13079a73
...@@ -72,7 +72,6 @@ ...@@ -72,7 +72,6 @@
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
...@@ -82,6 +81,7 @@ ...@@ -82,6 +81,7 @@
#define AT91SAM9RL_BASE_DMA 0xffffe600 #define AT91SAM9RL_BASE_DMA 0xffffe600
#define AT91SAM9RL_BASE_ECC 0xffffe800 #define AT91SAM9RL_BASE_ECC 0xffffe800
#define AT91SAM9RL_BASE_SMC 0xffffec00 #define AT91SAM9RL_BASE_SMC 0xffffec00
#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0
#define AT91SAM9RL_BASE_PIOA 0xfffff400 #define AT91SAM9RL_BASE_PIOA 0xfffff400
#define AT91SAM9RL_BASE_PIOB 0xfffff600 #define AT91SAM9RL_BASE_PIOB 0xfffff600
#define AT91SAM9RL_BASE_PIOC 0xfffff800 #define AT91SAM9RL_BASE_PIOC 0xfffff800
......
arch/arm/mach-at91/include/mach/debug-macro.S
View file @ 13079a73
...@@ -14,9 +14,15 @@ ...@@ -14,9 +14,15 @@
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/at91_dbgu.h> #include <mach/at91_dbgu.h>
#if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
#define AT91_DBGU AT91_BASE_DBGU0
#else
#define AT91_DBGU AT91_BASE_DBGU1
#endif
.macro addruart, rp, rv, tmp .macro addruart, rp, rv, tmp
ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) ldr \rp, =AT91_DBGU @ System peripherals (phys address)
ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address) ldr \rv, =AT91_IO_P2V(AT91_DBGU) @ System peripherals (virt address)
.endm .endm
.macro senduart,rd,rx .macro senduart,rd,rx
......
arch/arm/mach-at91/include/mach/hardware.h
View file @ 13079a73
...@@ -16,6 +16,12 @@ ...@@ -16,6 +16,12 @@
#include <asm/sizes.h> #include <asm/sizes.h>
/* DBGU base */
/* rm9200, 9260/9g20, 9261/9g10, 9rl */
#define AT91_BASE_DBGU0 0xfffff200
/* 9263, 9g45, cap9 */
#define AT91_BASE_DBGU1 0xffffee00
#if defined(CONFIG_ARCH_AT91RM9200) #if defined(CONFIG_ARCH_AT91RM9200)
#include <mach/at91rm9200.h> #include <mach/at91rm9200.h>
#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
......
arch/arm/mach-at91/include/mach/uncompress.h
View file @ 13079a73
...@@ -24,8 +24,10 @@ ...@@ -24,8 +24,10 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/atmel_serial.h> #include <linux/atmel_serial.h>
#if defined(CONFIG_AT91_EARLY_DBGU) #if defined(CONFIG_AT91_EARLY_DBGU0)
#define UART_OFFSET (AT91_DBGU + AT91_BASE_SYS) #define UART_OFFSET AT91_BASE_DBGU0
#elif defined(CONFIG_AT91_EARLY_DBGU1)
#define UART_OFFSET AT91_BASE_DBGU1
#elif defined(CONFIG_AT91_EARLY_USART0) #elif defined(CONFIG_AT91_EARLY_USART0)
#define UART_OFFSET AT91_USART0 #define UART_OFFSET AT91_USART0
#elif defined(CONFIG_AT91_EARLY_USART1) #elif defined(CONFIG_AT91_EARLY_USART1)
......
arch/arm/mach-at91/setup.c
View file @ 13079a73
...@@ -93,9 +93,6 @@ void at91_iounmap(volatile void __iomem *addr) ...@@ -93,9 +93,6 @@ void at91_iounmap(volatile void __iomem *addr)
} }
EXPORT_SYMBOL(at91_iounmap); EXPORT_SYMBOL(at91_iounmap);
#define AT91_DBGU0 0xfffff200
#define AT91_DBGU1 0xffffee00
static void __init soc_detect(u32 dbgu_base) static void __init soc_detect(u32 dbgu_base)
{ {
u32 cidr, socid; u32 cidr, socid;
...@@ -268,9 +265,9 @@ void __init at91_map_io(void) ...@@ -268,9 +265,9 @@ void __init at91_map_io(void)
at91_soc_initdata.type = AT91_SOC_NONE; at91_soc_initdata.type = AT91_SOC_NONE;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
soc_detect(AT91_DBGU0); soc_detect(AT91_BASE_DBGU0);
if (!at91_soc_is_detected()) if (!at91_soc_is_detected())
soc_detect(AT91_DBGU1); soc_detect(AT91_BASE_DBGU1);
if (!at91_soc_is_detected()) if (!at91_soc_is_detected())
panic("AT91: Impossible to detect the SOC type"); panic("AT91: Impossible to detect the SOC type");
......
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