Commit 130b4bd8 authored by Jerome Brunet's avatar Jerome Brunet Committed by Ulf Hansson

mmc: meson-gx: remove CLK_DIVIDER_ALLOW_ZERO clock flag

Remove CLK_DIVIDER_ALLOW_ZERO. This flag means that a 1 based divider
with a 0 value will behave as a bypass clock

The mmc divider does not behave like this, a 0 value disables the clock
Remove this flag so CCF never allows a 0 value on this clock

Fixes: 51c5d844 ("MMC: meson: initial support for GX platforms")
Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent c1d04caa
...@@ -389,7 +389,7 @@ static int meson_mmc_clk_init(struct meson_host *host) ...@@ -389,7 +389,7 @@ static int meson_mmc_clk_init(struct meson_host *host)
host->cfg_div.width = __builtin_popcountl(CLK_DIV_MASK); host->cfg_div.width = __builtin_popcountl(CLK_DIV_MASK);
host->cfg_div.hw.init = &init; host->cfg_div.hw.init = &init;
host->cfg_div.flags = CLK_DIVIDER_ONE_BASED | host->cfg_div.flags = CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ALLOW_ZERO; CLK_DIVIDER_ROUND_CLOSEST;
host->cfg_div_clk = devm_clk_register(host->dev, &host->cfg_div.hw); host->cfg_div_clk = devm_clk_register(host->dev, &host->cfg_div.hw);
if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk))) if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk)))
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment