Commit 1336028b authored by Joerg Roedel's avatar Joerg Roedel Committed by Avi Kivity

KVM: SVM: remove selective CR0 comment

There is not selective cr0 intercept bug. The code in the comment sets the
CR0.PG bit. But KVM sets the CR4.PG bit for SVM always to implement the paged
real mode. So the 'mov %eax,%cr0' instruction does not change the CR0.PG bit.
Selective CR0 intercepts only occur when a bit is actually changed. So its the
right behavior that there is no intercept on this instruction.
Signed-off-by: default avatarJoerg Roedel <joerg.roedel@amd.com>
Signed-off-by: default avatarAvi Kivity <avi@qumranet.com>
parent aaf697e4
...@@ -513,17 +513,6 @@ static void init_vmcb(struct vcpu_svm *svm) ...@@ -513,17 +513,6 @@ static void init_vmcb(struct vcpu_svm *svm)
control->intercept = (1ULL << INTERCEPT_INTR) | control->intercept = (1ULL << INTERCEPT_INTR) |
(1ULL << INTERCEPT_NMI) | (1ULL << INTERCEPT_NMI) |
(1ULL << INTERCEPT_SMI) | (1ULL << INTERCEPT_SMI) |
/*
* selective cr0 intercept bug?
* 0: 0f 22 d8 mov %eax,%cr3
* 3: 0f 20 c0 mov %cr0,%eax
* 6: 0d 00 00 00 80 or $0x80000000,%eax
* b: 0f 22 c0 mov %eax,%cr0
* set cr3 ->interception
* get cr0 ->interception
* set cr0 -> no interception
*/
/* (1ULL << INTERCEPT_SELECTIVE_CR0) | */
(1ULL << INTERCEPT_CPUID) | (1ULL << INTERCEPT_CPUID) |
(1ULL << INTERCEPT_INVD) | (1ULL << INTERCEPT_INVD) |
(1ULL << INTERCEPT_HLT) | (1ULL << INTERCEPT_HLT) |
......
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