clk: xgene: Fix divider with non-zero shift value
The X-Gene clock driver missed the divider shift operation when set the divider value. Signed-off-by: Loc Ho <lho@apm.com> Fixes: 308964ca ("clk: Add APM X-Gene SoC clock driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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