Commit 138a0764 authored by Michael Ellerman's avatar Michael Ellerman

Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux into next

Freescale updates from Scott:

"Contains include 86xx fixes, minor device tree fixes, an erratum
workaround, and a kconfig dependency fix."
parents 1d4e89cf 1eef33be
...@@ -797,7 +797,6 @@ config 4xx_SOC ...@@ -797,7 +797,6 @@ config 4xx_SOC
config FSL_LBC config FSL_LBC
bool "Freescale Local Bus support" bool "Freescale Local Bus support"
depends on FSL_SOC
help help
Enables reporting of errors from the Freescale local bus Enables reporting of errors from the Freescale local bus
controller. Also contains some common code used by controller. Also contains some common code used by
......
...@@ -362,9 +362,6 @@ $(obj)/cuImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits) ...@@ -362,9 +362,6 @@ $(obj)/cuImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
$(obj)/cuImage.%: vmlinux $(obj)/%.dtb $(wrapperbits) $(obj)/cuImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
$(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb) $(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb)
$(obj)/cuImage.%: vmlinux $(obj)/fsl/%.dtb $(wrapperbits)
$(call if_changed,wrap,cuboot-$*,,$(obj)/fsl/$*.dtb)
$(obj)/simpleImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits) $(obj)/simpleImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
$(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz) $(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
...@@ -381,6 +378,9 @@ $(obj)/treeImage.%: vmlinux $(obj)/%.dtb $(wrapperbits) ...@@ -381,6 +378,9 @@ $(obj)/treeImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
$(obj)/%.dtb: $(src)/dts/%.dts FORCE $(obj)/%.dtb: $(src)/dts/%.dts FORCE
$(call if_changed_dep,dtc) $(call if_changed_dep,dtc)
$(obj)/%.dtb: $(src)/dts/fsl/%.dts FORCE
$(call if_changed_dep,dtc)
# If there isn't a platform selected then just strip the vmlinux. # If there isn't a platform selected then just strip the vmlinux.
ifeq (,$(image-y)) ifeq (,$(image-y))
image-y := vmlinux.strip image-y := vmlinux.strip
......
...@@ -211,6 +211,10 @@ pcie@0 { ...@@ -211,6 +211,10 @@ pcie@0 {
0x0 0x00400000>; 0x0 0x00400000>;
}; };
}; };
pci1: pcie@fef09000 {
status = "disabled";
};
}; };
/include/ "mpc8641si-post.dtsi" /include/ "mpc8641si-post.dtsi"
...@@ -24,10 +24,6 @@ / { ...@@ -24,10 +24,6 @@ / {
model = "GEF_SBC310"; model = "GEF_SBC310";
compatible = "gef,sbc310"; compatible = "gef,sbc310";
aliases {
pci1 = &pci1;
};
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <0x0 0x40000000>; // set by uboot reg = <0x0 0x40000000>; // set by uboot
...@@ -223,29 +219,11 @@ pcie@0 { ...@@ -223,29 +219,11 @@ pcie@0 {
}; };
pci1: pcie@fef09000 { pci1: pcie@fef09000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
reg = <0xfef09000 0x1000>; reg = <0xfef09000 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>; 0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
clock-frequency = <100000000>;
interrupts = <0x19 0x2 0 0>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
0x0000 0x0 0x0 0x2 &mpic 0x5 0x2
0x0000 0x0 0x0 0x3 &mpic 0x6 0x2
0x0000 0x0 0x0 0x4 &mpic 0x7 0x2
>;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0xc0000000 ranges = <0x02000000 0x0 0xc0000000
0x02000000 0x0 0xc0000000 0x02000000 0x0 0xc0000000
0x0 0x20000000 0x0 0x20000000
......
...@@ -209,6 +209,10 @@ pcie@0 { ...@@ -209,6 +209,10 @@ pcie@0 {
0x0 0x00400000>; 0x0 0x00400000>;
}; };
}; };
pci1: pcie@fef09000 {
status = "disabled";
};
}; };
/include/ "mpc8641si-post.dtsi" /include/ "mpc8641si-post.dtsi"
...@@ -15,10 +15,6 @@ / { ...@@ -15,10 +15,6 @@ / {
model = "MPC8641HPCN"; model = "MPC8641HPCN";
compatible = "fsl,mpc8641hpcn"; compatible = "fsl,mpc8641hpcn";
aliases {
pci1 = &pci1;
};
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <0x00000000 0x40000000>; // 1G at 0x0 reg = <0x00000000 0x40000000>; // 1G at 0x0
...@@ -359,29 +355,11 @@ gpio@400 { ...@@ -359,29 +355,11 @@ gpio@400 {
}; };
pci1: pcie@ffe09000 { pci1: pcie@ffe09000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
reg = <0xffe09000 0x1000>; reg = <0xffe09000 0x1000>;
bus-range = <0 0xff>;
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>; 0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
clock-frequency = <100000000>;
interrupts = <25 2 0 0>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0x0000 0 0 1 &mpic 4 1
0x0000 0 0 2 &mpic 5 1
0x0000 0 0 3 &mpic 6 1
0x0000 0 0 4 &mpic 7 1
>;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0xa0000000 ranges = <0x02000000 0x0 0xa0000000
0x02000000 0x0 0xa0000000 0x02000000 0x0 0xa0000000
0x0 0x20000000 0x0 0x20000000
......
...@@ -17,10 +17,6 @@ / { ...@@ -17,10 +17,6 @@ / {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
aliases {
pci1 = &pci1;
};
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0 reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0
...@@ -326,29 +322,11 @@ gpio@400 { ...@@ -326,29 +322,11 @@ gpio@400 {
}; };
pci1: pcie@fffe09000 { pci1: pcie@fffe09000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
reg = <0x0f 0xffe09000 0x0 0x1000>; reg = <0x0f 0xffe09000 0x0 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000 ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>; 0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>;
clock-frequency = <100000000>;
interrupts = <25 2 0 0>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0x0000 0 0 1 &mpic 4 1
0x0000 0 0 2 &mpic 5 1
0x0000 0 0 3 &mpic 6 1
0x0000 0 0 4 &mpic 7 1
>;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0xe0000000 ranges = <0x02000000 0x0 0xe0000000
0x02000000 0x0 0xe0000000 0x02000000 0x0 0xe0000000
0x0 0x20000000 0x0 0x20000000
......
...@@ -102,19 +102,46 @@ &pci0 { ...@@ -102,19 +102,46 @@ &pci0 {
bus-range = <0x0 0xff>; bus-range = <0x0 0xff>;
clock-frequency = <100000000>; clock-frequency = <100000000>;
interrupts = <24 2 0 0>; interrupts = <24 2 0 0>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < pcie@0 {
0x0000 0x0 0x0 0x1 &mpic 0x0 0x1 reg = <0 0 0 0 0>;
0x0000 0x0 0x0 0x2 &mpic 0x1 0x1 #interrupt-cells = <1>;
0x0000 0x0 0x0 0x3 &mpic 0x2 0x1 #size-cells = <2>;
0x0000 0x0 0x0 0x4 &mpic 0x3 0x1 #address-cells = <3>;
>; device_type = "pci";
interrupts = <24 2 0 0>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
0x0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
0x0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
0x0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
>;
};
};
&pci1 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0x0 0xff>;
clock-frequency = <100000000>;
interrupts = <25 2 0 0>;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>; reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
device_type = "pci"; device_type = "pci";
interrupts = <25 2 0 0>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
0x0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
0x0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
0x0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
>;
}; };
}; };
...@@ -25,6 +25,7 @@ aliases { ...@@ -25,6 +25,7 @@ aliases {
serial0 = &serial0; serial0 = &serial0;
serial1 = &serial1; serial1 = &serial1;
pci0 = &pci0; pci0 = &pci0;
pci1 = &pci1;
}; };
cpus { cpus {
......
...@@ -19,10 +19,6 @@ / { ...@@ -19,10 +19,6 @@ / {
model = "SBC8641D"; model = "SBC8641D";
compatible = "wind,sbc8641"; compatible = "wind,sbc8641";
aliases {
pci1 = &pci1;
};
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <0x00000000 0x20000000>; // 512M at 0x0 reg = <0x00000000 0x20000000>; // 512M at 0x0
...@@ -165,30 +161,11 @@ pcie@0 { ...@@ -165,30 +161,11 @@ pcie@0 {
}; };
pci1: pcie@f8009000 { pci1: pcie@f8009000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
reg = <0xf8009000 0x1000>; reg = <0xf8009000 0x1000>;
bus-range = <0 0xff>;
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>; 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
clock-frequency = <100000000>;
interrupts = <25 2 0 0>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0x0000 0 0 1 &mpic 4 1
0x0000 0 0 2 &mpic 5 1
0x0000 0 0 3 &mpic 6 1
0x0000 0 0 4 &mpic 7 1
>;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0xa0000000 ranges = <0x02000000 0x0 0xa0000000
0x02000000 0x0 0xa0000000 0x02000000 0x0 0xa0000000
0x0 0x20000000 0x0 0x20000000
......
...@@ -263,7 +263,7 @@ mux1: mux1@20 { ...@@ -263,7 +263,7 @@ mux1: mux1@20 {
}; };
rcpm: global-utilities@e2000 { rcpm: global-utilities@e2000 {
compatible = "fsl,t1023-rcpm", "fsl,qoriq-rcpm-2.0"; compatible = "fsl,t1023-rcpm", "fsl,qoriq-rcpm-2.1";
reg = <0xe2000 0x1000>; reg = <0xe2000 0x1000>;
}; };
......
...@@ -472,7 +472,7 @@ mux3: mux3@60 { ...@@ -472,7 +472,7 @@ mux3: mux3@60 {
}; };
rcpm: global-utilities@e2000 { rcpm: global-utilities@e2000 {
compatible = "fsl,t1040-rcpm", "fsl,qoriq-rcpm-2.0"; compatible = "fsl,t1040-rcpm", "fsl,qoriq-rcpm-2.1";
reg = <0xe2000 0x1000>; reg = <0xe2000 0x1000>;
}; };
......
...@@ -109,7 +109,7 @@ spi@110000 { ...@@ -109,7 +109,7 @@ spi@110000 {
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "micron,n25q512a", "jedec,spi-nor"; compatible = "micron,n25q512ax3", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <10000000>; /* input clock */ spi-max-frequency = <10000000>; /* input clock */
}; };
......
...@@ -113,7 +113,7 @@ spi@110000 { ...@@ -113,7 +113,7 @@ spi@110000 {
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "micron,n25q512a", "jedec,spi-nor"; compatible = "micron,n25q512ax3", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <10000000>; /* input clock */ spi-max-frequency = <10000000>; /* input clock */
}; };
......
...@@ -37,6 +37,7 @@ ...@@ -37,6 +37,7 @@
#include <asm/pci-bridge.h> #include <asm/pci-bridge.h>
#include <asm/ppc-pci.h> #include <asm/ppc-pci.h>
#include <asm/machdep.h> #include <asm/machdep.h>
#include <asm/mpc85xx.h>
#include <asm/disassemble.h> #include <asm/disassemble.h>
#include <asm/ppc-opcode.h> #include <asm/ppc-opcode.h>
#include <sysdev/fsl_soc.h> #include <sysdev/fsl_soc.h>
...@@ -527,6 +528,8 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary) ...@@ -527,6 +528,8 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
u8 hdr_type, progif; u8 hdr_type, progif;
struct device_node *dev; struct device_node *dev;
struct ccsr_pci __iomem *pci; struct ccsr_pci __iomem *pci;
u16 temp;
u32 svr = mfspr(SPRN_SVR);
dev = pdev->dev.of_node; dev = pdev->dev.of_node;
...@@ -596,6 +599,27 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary) ...@@ -596,6 +599,27 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
if (fsl_pcie_check_link(hose)) if (fsl_pcie_check_link(hose))
hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
} else {
/*
* Set PBFR(PCI Bus Function Register)[10] = 1 to
* disable the combining of crossing cacheline
* boundary requests into one burst transaction.
* PCI-X operation is not affected.
* Fix erratum PCI 5 on MPC8548
*/
#define PCI_BUS_FUNCTION 0x44
#define PCI_BUS_FUNCTION_MDS 0x400 /* Master disable streaming */
if (((SVR_SOC_VER(svr) == SVR_8543) ||
(SVR_SOC_VER(svr) == SVR_8545) ||
(SVR_SOC_VER(svr) == SVR_8547) ||
(SVR_SOC_VER(svr) == SVR_8548)) &&
!early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) {
early_read_config_word(hose, 0, 0,
PCI_BUS_FUNCTION, &temp);
temp |= PCI_BUS_FUNCTION_MDS;
early_write_config_word(hose, 0, 0,
PCI_BUS_FUNCTION, temp);
}
} }
printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
......
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