Commit 14054fb1 authored by Grygorii Strashko's avatar Grygorii Strashko Committed by Tony Lindgren

ARM: dts: am4372: fix clock source for arm twd and global timers

ARM TWD and Global timer are clocked by PERIPHCLK which is MPU_CLK/2.
But now they are clocked by dpll_mpu_m2_ck == MPU_CLK and, as result.
Timekeeping core misbehaves. For example, execution of command
"sleep 5" will take 10 sec instead of 5.

Hence, fix it by adding mpu_periphclk ("fixed-factor-clock") and use
it for clocking ARM TWD and Global timer (same way as on OMAP4).

Cc: Tony Lindgren <tony@atomide.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Fixes:commit 8cbd4c2f ("arm: boot: dts: am4372: add ARM timers and SCU nodes")
Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: default avatarFelipe Balbi <balbi@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent fc827928
...@@ -74,7 +74,7 @@ global_timer: timer@48240200 { ...@@ -74,7 +74,7 @@ global_timer: timer@48240200 {
reg = <0x48240200 0x100>; reg = <0x48240200 0x100>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
clocks = <&dpll_mpu_m2_ck>; clocks = <&mpu_periphclk>;
}; };
local_timer: timer@48240600 { local_timer: timer@48240600 {
...@@ -82,7 +82,7 @@ local_timer: timer@48240600 { ...@@ -82,7 +82,7 @@ local_timer: timer@48240600 {
reg = <0x48240600 0x100>; reg = <0x48240600 0x100>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
clocks = <&dpll_mpu_m2_ck>; clocks = <&mpu_periphclk>;
}; };
l2-cache-controller@48242000 { l2-cache-controller@48242000 {
......
...@@ -259,6 +259,14 @@ dpll_mpu_m2_ck: dpll_mpu_m2_ck { ...@@ -259,6 +259,14 @@ dpll_mpu_m2_ck: dpll_mpu_m2_ck {
ti,invert-autoidle-bit; ti,invert-autoidle-bit;
}; };
mpu_periphclk: mpu_periphclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_mpu_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
dpll_ddr_ck: dpll_ddr_ck { dpll_ddr_ck: dpll_ddr_ck {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,am3-dpll-clock"; compatible = "ti,am3-dpll-clock";
......
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