Commit 14328aa5 authored by Philip Cox's avatar Philip Cox Committed by Alex Deucher

drm/amdkfd: Add navi10 support to amdkfd. (v3)

KFD (kernel fusion driver) is the kernel driver
for the compute backend for usermode compute
stack.

v2: squash in updates (Alex)
v3: squash in rebase fixes (Alex)
Signed-off-by: default avatarOak Zeng <Oak.Zeng@amd.com>
Signed-off-by: default avatarPhilip Cox <Philip.Cox@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e0d07657
...@@ -693,6 +693,14 @@ MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (defau ...@@ -693,6 +693,14 @@ MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (defau
bool hws_gws_support; bool hws_gws_support;
module_param(hws_gws_support, bool, 0444); module_param(hws_gws_support, bool, 0444);
MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)"); MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)");
/**
* DOC: queue_preemption_timeout_ms (int)
* queue preemption timeout in ms (1 = Minimum, 9000 = default)
*/
int queue_preemption_timeout_ms;
module_param(queue_preemption_timeout_ms, int, 0644);
MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
#endif #endif
/** /**
......
...@@ -36,16 +36,19 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ ...@@ -36,16 +36,19 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \
$(AMDKFD_PATH)/kfd_mqd_manager_cik.o \ $(AMDKFD_PATH)/kfd_mqd_manager_cik.o \
$(AMDKFD_PATH)/kfd_mqd_manager_vi.o \ $(AMDKFD_PATH)/kfd_mqd_manager_vi.o \
$(AMDKFD_PATH)/kfd_mqd_manager_v9.o \ $(AMDKFD_PATH)/kfd_mqd_manager_v9.o \
$(AMDKFD_PATH)/kfd_mqd_manager_v10.o \
$(AMDKFD_PATH)/kfd_kernel_queue.o \ $(AMDKFD_PATH)/kfd_kernel_queue.o \
$(AMDKFD_PATH)/kfd_kernel_queue_cik.o \ $(AMDKFD_PATH)/kfd_kernel_queue_cik.o \
$(AMDKFD_PATH)/kfd_kernel_queue_vi.o \ $(AMDKFD_PATH)/kfd_kernel_queue_vi.o \
$(AMDKFD_PATH)/kfd_kernel_queue_v9.o \ $(AMDKFD_PATH)/kfd_kernel_queue_v9.o \
$(AMDKFD_PATH)/kfd_kernel_queue_v10.o \
$(AMDKFD_PATH)/kfd_packet_manager.o \ $(AMDKFD_PATH)/kfd_packet_manager.o \
$(AMDKFD_PATH)/kfd_process_queue_manager.o \ $(AMDKFD_PATH)/kfd_process_queue_manager.o \
$(AMDKFD_PATH)/kfd_device_queue_manager.o \ $(AMDKFD_PATH)/kfd_device_queue_manager.o \
$(AMDKFD_PATH)/kfd_device_queue_manager_cik.o \ $(AMDKFD_PATH)/kfd_device_queue_manager_cik.o \
$(AMDKFD_PATH)/kfd_device_queue_manager_vi.o \ $(AMDKFD_PATH)/kfd_device_queue_manager_vi.o \
$(AMDKFD_PATH)/kfd_device_queue_manager_v9.o \ $(AMDKFD_PATH)/kfd_device_queue_manager_v9.o \
$(AMDKFD_PATH)/kfd_device_queue_manager_v10.o \
$(AMDKFD_PATH)/kfd_interrupt.o \ $(AMDKFD_PATH)/kfd_interrupt.o \
$(AMDKFD_PATH)/kfd_events.o \ $(AMDKFD_PATH)/kfd_events.o \
$(AMDKFD_PATH)/cik_event_interrupt.o \ $(AMDKFD_PATH)/cik_event_interrupt.o \
......
...@@ -561,3 +561,302 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { ...@@ -561,3 +561,302 @@ static const uint32_t cwsr_trap_gfx9_hex[] = {
0xbf8a0000, 0x95806f6c, 0xbf8a0000, 0x95806f6c,
0xbf810000, 0x00000000, 0xbf810000, 0x00000000,
}; };
static const uint32_t cwsr_trap_gfx10_hex[] = {
0xbf820001, 0xbf82012e,
0xb0804004, 0xb970f802,
0x8a708670, 0xb971f803,
0x8771ff71, 0x00000400,
0xbf850008, 0xb971f803,
0x8771ff71, 0x000001ff,
0xbf850001, 0x806c846c,
0x876dff6d, 0x0000ffff,
0xbe80226c, 0xb971f803,
0x8771ff71, 0x00000100,
0xbf840006, 0xbef60380,
0xb9f60203, 0x876dff6d,
0x0000ffff, 0x80ec886c,
0x82ed806d, 0xbef60380,
0xb9f60283, 0xb973f816,
0xb9762c07, 0x8f769c76,
0x886d766d, 0xb97603c7,
0x8f769b76, 0x886d766d,
0xb976f807, 0x8776ff76,
0x00007fff, 0xb9f6f807,
0xbeee037e, 0xbeef037f,
0xbefe0480, 0xbf900004,
0xbf8e0002, 0xbf88fffe,
0xbef4037e, 0x8775ff7f,
0x0000ffff, 0x8875ff75,
0x00040000, 0xbef60380,
0xbef703ff, 0x00807fac,
0x8776ff7f, 0x08000000,
0x90768376, 0x88777677,
0x8776ff7f, 0x70000000,
0x90768176, 0x88777677,
0xbefb037c, 0xbefa0380,
0xb97202dc, 0x8872727f,
0xbefe03c1, 0x877c8172,
0xbf06817c, 0xbf850002,
0xbeff0380, 0xbf820001,
0xbeff03c1, 0xb9712a05,
0x80718171, 0x8f718271,
0x877c8172, 0xbf06817c,
0xbf85000d, 0x8f768771,
0xbef603ff, 0x01000000,
0xbefc0380, 0x7e008700,
0xe0704000, 0x7a5d0000,
0x807c817c, 0x807aff7a,
0x00000080, 0xbf0a717c,
0xbf85fff8, 0xbf82001b,
0x8f768871, 0xbef603ff,
0x01000000, 0xbefc0380,
0x7e008700, 0xe0704000,
0x7a5d0000, 0x807c817c,
0x807aff7a, 0x00000100,
0xbf0a717c, 0xbf85fff8,
0xb9711e06, 0x8771c171,
0xbf84000c, 0x8f718371,
0x80717c71, 0xbefe03c1,
0xbeff0380, 0x7e008700,
0xe0704000, 0x7a5d0000,
0x807c817c, 0x807aff7a,
0x00000080, 0xbf0a717c,
0xbf85fff8, 0xbf8a0000,
0x8776ff72, 0x04000000,
0xbf84002b, 0xbefe03c1,
0x877c8172, 0xbf06817c,
0xbf850002, 0xbeff0380,
0xbf820001, 0xbeff03c1,
0xb9714306, 0x8771c171,
0xbf840021, 0x8f718671,
0x8f718271, 0xbef60371,
0xbef603ff, 0x01000000,
0xd7650000, 0x000100c1,
0xd7660000, 0x000200c1,
0x16000084, 0x877c8172,
0xbf06817c, 0xbefc0380,
0xbf85000a, 0x807cff7c,
0x00000080, 0x807aff7a,
0x00000080, 0xd5250000,
0x0001ff00, 0x00000080,
0xbf0a717c, 0xbf85fff7,
0xbf820009, 0x807cff7c,
0x00000100, 0x807aff7a,
0x00000100, 0xd5250000,
0x0001ff00, 0x00000100,
0xbf0a717c, 0xbf85fff7,
0x877c8172, 0xbf06817c,
0xbf850003, 0x8f7687ff,
0x0000006a, 0xbf820002,
0x8f7688ff, 0x0000006a,
0xbef603ff, 0x01000000,
0x877c8172, 0xbf06817c,
0xbefc0380, 0xbf800000,
0xbf85000b, 0xbe802e00,
0x7e000200, 0xe0704000,
0x7a5d0000, 0x807aff7a,
0x00000080, 0x807c817c,
0xbf0aff7c, 0x0000006a,
0xbf85fff6, 0xbf82000a,
0xbe802e00, 0x7e000200,
0xe0704000, 0x7a5d0000,
0x807aff7a, 0x00000100,
0x807c817c, 0xbf0aff7c,
0x0000006a, 0xbf85fff6,
0xbef60384, 0xbef603ff,
0x01000000, 0x877c8172,
0xbf06817c, 0xbf850030,
0x7e00027b, 0xe0704000,
0x7a5d0000, 0x807aff7a,
0x00000080, 0x7e00026c,
0xe0704000, 0x7a5d0000,
0x807aff7a, 0x00000080,
0x7e00026d, 0xe0704000,
0x7a5d0000, 0x807aff7a,
0x00000080, 0x7e00026e,
0xe0704000, 0x7a5d0000,
0x807aff7a, 0x00000080,
0x7e00026f, 0xe0704000,
0x7a5d0000, 0x807aff7a,
0x00000080, 0x7e000270,
0xe0704000, 0x7a5d0000,
0x807aff7a, 0x00000080,
0xb971f803, 0x7e000271,
0xe0704000, 0x7a5d0000,
0x807aff7a, 0x00000080,
0x7e000273, 0xe0704000,
0x7a5d0000, 0x807aff7a,
0x00000080, 0xb97bf801,
0x7e00027b, 0xe0704000,
0x7a5d0000, 0x807aff7a,
0x00000080, 0xbf82002f,
0x7e00027b, 0xe0704000,
0x7a5d0000, 0x807aff7a,
0x00000100, 0x7e00026c,
0xe0704000, 0x7a5d0000,
0x807aff7a, 0x00000100,
0x7e00026d, 0xe0704000,
0x7a5d0000, 0x807aff7a,
0x00000100, 0x7e00026e,
0xe0704000, 0x7a5d0000,
0x807aff7a, 0x00000100,
0x7e00026f, 0xe0704000,
0x7a5d0000, 0x807aff7a,
0x00000100, 0x7e000270,
0xe0704000, 0x7a5d0000,
0x807aff7a, 0x00000100,
0xb971f803, 0x7e000271,
0xe0704000, 0x7a5d0000,
0x807aff7a, 0x00000100,
0x7e000273, 0xe0704000,
0x7a5d0000, 0x807aff7a,
0x00000100, 0xb97bf801,
0x7e00027b, 0xe0704000,
0x7a5d0000, 0x807aff7a,
0x00000100, 0xbf820119,
0xbef4037e, 0x8775ff7f,
0x0000ffff, 0x8875ff75,
0x00040000, 0xbef60380,
0xbef703ff, 0x00807fac,
0x8772ff7f, 0x08000000,
0x90728372, 0x88777277,
0x8772ff7f, 0x70000000,
0x90728172, 0x88777277,
0xb97902dc, 0x8879797f,
0xbef80380, 0xbefe03c1,
0x877c8179, 0xbf06817c,
0xbf850002, 0xbeff0380,
0xbf820001, 0xbeff03c1,
0xb96f2a05, 0x806f816f,
0x8f6f826f, 0x877c8179,
0xbf06817c, 0xbf850013,
0x8f76876f, 0xbef603ff,
0x01000000, 0xbef20378,
0x8078ff78, 0x00000080,
0xbefc0381, 0xe0304000,
0x785d0000, 0xbf8c3f70,
0x7e008500, 0x807c817c,
0x8078ff78, 0x00000080,
0xbf0a6f7c, 0xbf85fff7,
0xe0304000, 0x725d0000,
0xbf820023, 0x8f76886f,
0xbef603ff, 0x01000000,
0xbef20378, 0x8078ff78,
0x00000100, 0xbefc0381,
0xe0304000, 0x785d0000,
0xbf8c3f70, 0x7e008500,
0x807c817c, 0x8078ff78,
0x00000100, 0xbf0a6f7c,
0xbf85fff7, 0xb96f1e06,
0x876fc16f, 0xbf84000e,
0x8f6f836f, 0x806f7c6f,
0xbefe03c1, 0xbeff0380,
0xe0304000, 0x785d0000,
0xbf8c3f70, 0x7e008500,
0x807c817c, 0x8078ff78,
0x00000080, 0xbf0a6f7c,
0xbf85fff7, 0xbeff03c1,
0xe0304000, 0x725d0000,
0x8772ff79, 0x04000000,
0xbf840020, 0xbefe03c1,
0x877c8179, 0xbf06817c,
0xbf850002, 0xbeff0380,
0xbf820001, 0xbeff03c1,
0xb96f4306, 0x876fc16f,
0xbf840016, 0x8f6f866f,
0x8f6f826f, 0xbef6036f,
0xbef603ff, 0x01000000,
0x877c8172, 0xbf06817c,
0xbefc0380, 0xbf850007,
0x807cff7c, 0x00000080,
0x8078ff78, 0x00000080,
0xbf0a6f7c, 0xbf85fffa,
0xbf820006, 0x807cff7c,
0x00000100, 0x8078ff78,
0x00000100, 0xbf0a6f7c,
0xbf85fffa, 0x877c8179,
0xbf06817c, 0xbf850003,
0x8f7687ff, 0x0000006a,
0xbf820002, 0x8f7688ff,
0x0000006a, 0xbef603ff,
0x01000000, 0x877c8179,
0xbf06817c, 0xbf850012,
0xf4211cba, 0xf0000000,
0x8078ff78, 0x00000080,
0xbefc0381, 0xf421003a,
0xf0000000, 0x8078ff78,
0x00000080, 0xbf8cc07f,
0xbe803000, 0xbf800000,
0x807c817c, 0xbf0aff7c,
0x0000006a, 0xbf85fff5,
0xbe800372, 0xbf820011,
0xf4211cba, 0xf0000000,
0x8078ff78, 0x00000100,
0xbefc0381, 0xf421003a,
0xf0000000, 0x8078ff78,
0x00000100, 0xbf8cc07f,
0xbe803000, 0xbf800000,
0x807c817c, 0xbf0aff7c,
0x0000006a, 0xbf85fff5,
0xbe800372, 0xbef60384,
0xbef603ff, 0x01000000,
0x877c8179, 0xbf06817c,
0xbf850025, 0xf4211bfa,
0xf0000000, 0x8078ff78,
0x00000080, 0xf4211b3a,
0xf0000000, 0x8078ff78,
0x00000080, 0xf4211b7a,
0xf0000000, 0x8078ff78,
0x00000080, 0xf4211eba,
0xf0000000, 0x8078ff78,
0x00000080, 0xf4211efa,
0xf0000000, 0x8078ff78,
0x00000080, 0xf4211c3a,
0xf0000000, 0x8078ff78,
0x00000080, 0xf4211c7a,
0xf0000000, 0x8078ff78,
0x00000080, 0xf4211cfa,
0xf0000000, 0x8078ff78,
0x00000080, 0xf4211e7a,
0xf0000000, 0x8078ff78,
0x00000080, 0xbf820024,
0xf4211bfa, 0xf0000000,
0x8078ff78, 0x00000100,
0xf4211b3a, 0xf0000000,
0x8078ff78, 0x00000100,
0xf4211b7a, 0xf0000000,
0x8078ff78, 0x00000100,
0xf4211eba, 0xf0000000,
0x8078ff78, 0x00000100,
0xf4211efa, 0xf0000000,
0x8078ff78, 0x00000100,
0xf4211c3a, 0xf0000000,
0x8078ff78, 0x00000100,
0xf4211c7a, 0xf0000000,
0x8078ff78, 0x00000100,
0xf4211cfa, 0xf0000000,
0x8078ff78, 0x00000100,
0xf4211e7a, 0xf0000000,
0x8078ff78, 0x00000100,
0xbf8cc07f, 0x876dff6d,
0x0000ffff, 0xbefc036f,
0xbefe037a, 0xbeff037b,
0x876f71ff, 0x000003ff,
0xb9ef4803, 0xb9f3f816,
0x876f71ff, 0xfffff800,
0x906f8b6f, 0xb9efa2c3,
0xb9f9f801, 0x876fff6d,
0xf0000000, 0x906f9c6f,
0x8f6f906f, 0xbef20380,
0x88726f72, 0x876fff6d,
0x08000000, 0x906f9b6f,
0x8f6f8f6f, 0x88726f72,
0x876fff70, 0x00800000,
0x906f976f, 0xb9f2f807,
0xb9f0f802, 0xbf8a0000,
0xbe80226c, 0xbf810000,
0xbf9f0000, 0xbf9f0000,
0xbf9f0000, 0xbf9f0000,
0xbf9f0000, 0x00000000,
};
This diff is collapsed.
...@@ -138,6 +138,8 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = { ...@@ -138,6 +138,8 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
/* TODO - check & update Vega10 cache details */ /* TODO - check & update Vega10 cache details */
#define vega10_cache_info carrizo_cache_info #define vega10_cache_info carrizo_cache_info
#define raven_cache_info carrizo_cache_info #define raven_cache_info carrizo_cache_info
/* TODO - check & update Navi10 cache details */
#define navi10_cache_info carrizo_cache_info
static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev, static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
struct crat_subtype_computeunit *cu) struct crat_subtype_computeunit *cu)
...@@ -666,6 +668,9 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev, ...@@ -666,6 +668,9 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
case CHIP_RAVEN: case CHIP_RAVEN:
pcache_info = raven_cache_info; pcache_info = raven_cache_info;
num_of_cache_types = ARRAY_SIZE(raven_cache_info); num_of_cache_types = ARRAY_SIZE(raven_cache_info);
case CHIP_NAVI10:
pcache_info = navi10_cache_info;
num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
break; break;
default: default:
return -EINVAL; return -EINVAL;
......
...@@ -317,6 +317,23 @@ static const struct kfd_device_info vega20_device_info = { ...@@ -317,6 +317,23 @@ static const struct kfd_device_info vega20_device_info = {
.num_sdma_queues_per_engine = 8, .num_sdma_queues_per_engine = 8,
}; };
static const struct kfd_device_info navi10_device_info = {
.asic_family = CHIP_NAVI10,
.max_pasid_bits = 16,
.max_no_of_hqd = 24,
.doorbell_size = 8,
.ih_ring_entry_size = 8 * sizeof(uint32_t),
.event_interrupt_class = &event_interrupt_class_v9,
.num_of_watch_points = 4,
.mqd_size_aligned = MQD_SIZE_ALIGNED,
.needs_iommu_device = false,
.supports_cwsr = true,
.needs_pci_atomics = false,
.num_sdma_engines = 2,
.num_xgmi_sdma_engines = 0,
.num_sdma_queues_per_engine = 8,
};
struct kfd_deviceid { struct kfd_deviceid {
unsigned short did; unsigned short did;
const struct kfd_device_info *device_info; const struct kfd_device_info *device_info;
...@@ -434,7 +451,13 @@ static const struct kfd_deviceid supported_devices[] = { ...@@ -434,7 +451,13 @@ static const struct kfd_deviceid supported_devices[] = {
{ 0x66a3, &vega20_device_info }, /* Vega20 */ { 0x66a3, &vega20_device_info }, /* Vega20 */
{ 0x66a4, &vega20_device_info }, /* Vega20 */ { 0x66a4, &vega20_device_info }, /* Vega20 */
{ 0x66a7, &vega20_device_info }, /* Vega20 */ { 0x66a7, &vega20_device_info }, /* Vega20 */
{ 0x66af, &vega20_device_info } /* Vega20 */ { 0x66af, &vega20_device_info }, /* Vega20 */
/* Navi10 */
{ 0x7310, &navi10_device_info }, /* Navi10 */
{ 0x7312, &navi10_device_info }, /* Navi10 */
{ 0x7318, &navi10_device_info }, /* Navi10 */
{ 0x731a, &navi10_device_info }, /* Navi10 */
{ 0x731f, &navi10_device_info }, /* Navi10 */
}; };
static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
...@@ -516,10 +539,14 @@ static void kfd_cwsr_init(struct kfd_dev *kfd) ...@@ -516,10 +539,14 @@ static void kfd_cwsr_init(struct kfd_dev *kfd)
BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
kfd->cwsr_isa = cwsr_trap_gfx8_hex; kfd->cwsr_isa = cwsr_trap_gfx8_hex;
kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
} else { } else if (kfd->device_info->asic_family < CHIP_NAVI10) {
BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
kfd->cwsr_isa = cwsr_trap_gfx9_hex; kfd->cwsr_isa = cwsr_trap_gfx9_hex;
kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
} else {
BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE);
kfd->cwsr_isa = cwsr_trap_gfx10_hex;
kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
} }
kfd->cwsr_enabled = true; kfd->cwsr_enabled = true;
......
...@@ -1264,6 +1264,7 @@ static int map_queues_cpsch(struct device_queue_manager *dqm) ...@@ -1264,6 +1264,7 @@ static int map_queues_cpsch(struct device_queue_manager *dqm)
return 0; return 0;
retval = pm_send_runlist(&dqm->packets, &dqm->queues); retval = pm_send_runlist(&dqm->packets, &dqm->queues);
pr_debug("%s sent runlist\n", __func__);
if (retval) { if (retval) {
pr_err("failed to execute runlist\n"); pr_err("failed to execute runlist\n");
return retval; return retval;
...@@ -1301,7 +1302,7 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm, ...@@ -1301,7 +1302,7 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm,
KFD_FENCE_COMPLETED); KFD_FENCE_COMPLETED);
/* should be timed out */ /* should be timed out */
retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED, retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS); queue_preemption_timeout_ms);
if (retval) if (retval)
return retval; return retval;
...@@ -1785,6 +1786,9 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) ...@@ -1785,6 +1786,9 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
case CHIP_RAVEN: case CHIP_RAVEN:
device_queue_manager_init_v9(&dqm->asic_ops); device_queue_manager_init_v9(&dqm->asic_ops);
break; break;
case CHIP_NAVI10:
device_queue_manager_init_v10_navi10(&dqm->asic_ops);
break;
default: default:
WARN(1, "Unexpected ASIC family %u", WARN(1, "Unexpected ASIC family %u",
dev->device_info->asic_family); dev->device_info->asic_family);
...@@ -1876,12 +1880,13 @@ int dqm_debugfs_hqds(struct seq_file *m, void *data) ...@@ -1876,12 +1880,13 @@ int dqm_debugfs_hqds(struct seq_file *m, void *data)
int r = 0; int r = 0;
r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->kgd, r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->kgd,
KFD_CIK_HIQ_PIPE, KFD_CIK_HIQ_QUEUE, &dump, &n_regs); KFD_CIK_HIQ_PIPE, KFD_CIK_HIQ_QUEUE,
&dump, &n_regs);
if (!r) { if (!r) {
seq_printf(m, " HIQ on MEC %d Pipe %d Queue %d\n", seq_printf(m, " HIQ on MEC %d Pipe %d Queue %d\n",
KFD_CIK_HIQ_PIPE/get_pipes_per_mec(dqm)+1, KFD_CIK_HIQ_PIPE/get_pipes_per_mec(dqm)+1,
KFD_CIK_HIQ_PIPE%get_pipes_per_mec(dqm), KFD_CIK_HIQ_PIPE%get_pipes_per_mec(dqm),
KFD_CIK_HIQ_QUEUE); KFD_CIK_HIQ_QUEUE);
seq_reg_dump(m, dump, n_regs); seq_reg_dump(m, dump, n_regs);
kfree(dump); kfree(dump);
......
...@@ -31,8 +31,6 @@ ...@@ -31,8 +31,6 @@
#include "kfd_priv.h" #include "kfd_priv.h"
#include "kfd_mqd_manager.h" #include "kfd_mqd_manager.h"
#define KFD_UNMAP_LATENCY_MS (4000)
#define QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS (2 * KFD_UNMAP_LATENCY_MS + 1000)
struct device_process_node { struct device_process_node {
struct qcm_process_device *qpd; struct qcm_process_device *qpd;
...@@ -212,6 +210,8 @@ void device_queue_manager_init_vi_tonga( ...@@ -212,6 +210,8 @@ void device_queue_manager_init_vi_tonga(
struct device_queue_manager_asic_ops *asic_ops); struct device_queue_manager_asic_ops *asic_ops);
void device_queue_manager_init_v9( void device_queue_manager_init_v9(
struct device_queue_manager_asic_ops *asic_ops); struct device_queue_manager_asic_ops *asic_ops);
void device_queue_manager_init_v10_navi10(
struct device_queue_manager_asic_ops *asic_ops);
void program_sh_mem_settings(struct device_queue_manager *dqm, void program_sh_mem_settings(struct device_queue_manager *dqm,
struct qcm_process_device *qpd); struct qcm_process_device *qpd);
unsigned int get_queues_num(struct device_queue_manager *dqm); unsigned int get_queues_num(struct device_queue_manager *dqm);
......
/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "kfd_device_queue_manager.h"
#include "navi10_enum.h"
#include "gc/gc_10_1_0_offset.h"
#include "gc/gc_10_1_0_sh_mask.h"
static int update_qpd_v10(struct device_queue_manager *dqm,
struct qcm_process_device *qpd);
static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q,
struct qcm_process_device *qpd);
void device_queue_manager_init_v10_navi10(
struct device_queue_manager_asic_ops *asic_ops)
{
asic_ops->update_qpd = update_qpd_v10;
asic_ops->init_sdma_vm = init_sdma_vm_v10;
asic_ops->mqd_manager_init = mqd_manager_init_v10;
}
static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
{
uint32_t shared_base = pdd->lds_base >> 48;
uint32_t private_base = pdd->scratch_base >> 48;
return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) |
private_base;
}
static int update_qpd_v10(struct device_queue_manager *dqm,
struct qcm_process_device *qpd)
{
struct kfd_process_device *pdd;
pdd = qpd_to_pdd(qpd);
/* check if sh_mem_config register already configured */
if (qpd->sh_mem_config == 0) {
qpd->sh_mem_config =
SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
#if 0
/* TODO:
* This shouldn't be an issue with Navi10. Verify.
*/
if (vega10_noretry)
qpd->sh_mem_config |=
1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
#endif
qpd->sh_mem_ape1_limit = 0;
qpd->sh_mem_ape1_base = 0;
}
qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
return 0;
}
static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q,
struct qcm_process_device *qpd)
{
/* Not needed on SDMAv4 onwards any more */
q->properties.sdma_vm_addr = 0;
}
...@@ -405,6 +405,7 @@ int kfd_init_apertures(struct kfd_process *process) ...@@ -405,6 +405,7 @@ int kfd_init_apertures(struct kfd_process *process)
case CHIP_VEGA12: case CHIP_VEGA12:
case CHIP_VEGA20: case CHIP_VEGA20:
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_NAVI10:
kfd_init_apertures_v9(pdd, id); kfd_init_apertures_v9(pdd, id);
break; break;
default: default:
......
...@@ -332,6 +332,9 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev, ...@@ -332,6 +332,9 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
case CHIP_RAVEN: case CHIP_RAVEN:
kernel_queue_init_v9(&kq->ops_asic_specific); kernel_queue_init_v9(&kq->ops_asic_specific);
break; break;
case CHIP_NAVI10:
kernel_queue_init_v10(&kq->ops_asic_specific);
break;
default: default:
WARN(1, "Unexpected ASIC family %u", WARN(1, "Unexpected ASIC family %u",
dev->device_info->asic_family); dev->device_info->asic_family);
......
...@@ -102,5 +102,6 @@ struct kernel_queue { ...@@ -102,5 +102,6 @@ struct kernel_queue {
void kernel_queue_init_cik(struct kernel_queue_ops *ops); void kernel_queue_init_cik(struct kernel_queue_ops *ops);
void kernel_queue_init_vi(struct kernel_queue_ops *ops); void kernel_queue_init_vi(struct kernel_queue_ops *ops);
void kernel_queue_init_v9(struct kernel_queue_ops *ops); void kernel_queue_init_v9(struct kernel_queue_ops *ops);
void kernel_queue_init_v10(struct kernel_queue_ops *ops);
#endif /* KFD_KERNEL_QUEUE_H_ */ #endif /* KFD_KERNEL_QUEUE_H_ */
This diff is collapsed.
This diff is collapsed.
...@@ -237,6 +237,9 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm) ...@@ -237,6 +237,9 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
case CHIP_RAVEN: case CHIP_RAVEN:
pm->pmf = &kfd_v9_pm_funcs; pm->pmf = &kfd_v9_pm_funcs;
break; break;
case CHIP_NAVI10:
pm->pmf = &kfd_v10_pm_funcs;
break;
default: default:
WARN(1, "Unexpected ASIC family %u", WARN(1, "Unexpected ASIC family %u",
dqm->dev->device_info->asic_family); dqm->dev->device_info->asic_family);
......
...@@ -105,6 +105,8 @@ ...@@ -105,6 +105,8 @@
#define KFD_KERNEL_QUEUE_SIZE 2048 #define KFD_KERNEL_QUEUE_SIZE 2048
#define KFD_UNMAP_LATENCY_MS (4000)
/* /*
* 512 = 0x200 * 512 = 0x200
* The doorbell index distance between SDMA RLC (2*i) and (2*i+1) in the * The doorbell index distance between SDMA RLC (2*i) and (2*i+1) in the
...@@ -167,11 +169,20 @@ extern int halt_if_hws_hang; ...@@ -167,11 +169,20 @@ extern int halt_if_hws_hang;
*/ */
extern bool hws_gws_support; extern bool hws_gws_support;
/*
* Queue preemption timeout in ms
*/
extern int queue_preemption_timeout_ms;
enum cache_policy { enum cache_policy {
cache_policy_coherent, cache_policy_coherent,
cache_policy_noncoherent cache_policy_noncoherent
}; };
#define KFD_IS_VI(chip) ((chip) >= CHIP_CARRIZO && (chip) <= CHIP_POLARIS11)
#define KFD_IS_DGPU(chip) (((chip) >= CHIP_TONGA && \
(chip) <= CHIP_NAVI10) || \
(chip) == CHIP_HAWAII)
#define KFD_IS_SOC15(chip) ((chip) >= CHIP_VEGA10) #define KFD_IS_SOC15(chip) ((chip) >= CHIP_VEGA10)
struct kfd_event_interrupt_class { struct kfd_event_interrupt_class {
...@@ -870,6 +881,8 @@ struct mqd_manager *mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type, ...@@ -870,6 +881,8 @@ struct mqd_manager *mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type,
struct kfd_dev *dev); struct kfd_dev *dev);
struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
struct kfd_dev *dev); struct kfd_dev *dev);
struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
struct kfd_dev *dev);
struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev); struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev);
void device_queue_manager_uninit(struct device_queue_manager *dqm); void device_queue_manager_uninit(struct device_queue_manager *dqm);
struct kernel_queue *kernel_queue_init(struct kfd_dev *dev, struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
...@@ -909,8 +922,8 @@ int pqm_get_wave_state(struct process_queue_manager *pqm, ...@@ -909,8 +922,8 @@ int pqm_get_wave_state(struct process_queue_manager *pqm,
u32 *save_area_used_size); u32 *save_area_used_size);
int amdkfd_fence_wait_timeout(unsigned int *fence_addr, int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
unsigned int fence_value, unsigned int fence_value,
unsigned int timeout_ms); unsigned int timeout_ms);
/* Packet Manager */ /* Packet Manager */
...@@ -959,6 +972,7 @@ struct packet_manager_funcs { ...@@ -959,6 +972,7 @@ struct packet_manager_funcs {
extern const struct packet_manager_funcs kfd_vi_pm_funcs; extern const struct packet_manager_funcs kfd_vi_pm_funcs;
extern const struct packet_manager_funcs kfd_v9_pm_funcs; extern const struct packet_manager_funcs kfd_v9_pm_funcs;
extern const struct packet_manager_funcs kfd_v10_pm_funcs;
int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm); int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm);
void pm_uninit(struct packet_manager *pm); void pm_uninit(struct packet_manager *pm);
...@@ -978,7 +992,8 @@ void pm_release_ib(struct packet_manager *pm); ...@@ -978,7 +992,8 @@ void pm_release_ib(struct packet_manager *pm);
/* Following PM funcs can be shared among VI and AI */ /* Following PM funcs can be shared among VI and AI */
unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size); unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size);
int pm_set_resources_vi(struct packet_manager *pm, uint32_t *buffer, int pm_set_resources_vi(struct packet_manager *pm, uint32_t *buffer,
struct scheduling_resources *res); struct scheduling_resources *res);
uint64_t kfd_get_number_elems(struct kfd_dev *kfd); uint64_t kfd_get_number_elems(struct kfd_dev *kfd);
......
...@@ -1203,3 +1203,4 @@ int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data) ...@@ -1203,3 +1203,4 @@ int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data)
} }
#endif #endif
...@@ -1321,6 +1321,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu) ...@@ -1321,6 +1321,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
case CHIP_VEGA12: case CHIP_VEGA12:
case CHIP_VEGA20: case CHIP_VEGA20:
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_NAVI10:
dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 << dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) & HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK); HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
......
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