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Commit 14a44ab0 authored by Russell King (Oracle)'s avatar Russell King (Oracle) Committed by Jakub Kicinski
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net: mtk_eth_soc: partially convert to phylink_pcs 

Partially convert mtk_eth_soc to phylink_pcs, moving the configuration,
link up and AN restart over. However, it seems mac_pcs_get_state()
doesn't actually get the state from the PCS, so we can't convert that
over without a better understanding of the hardware.
Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 901f3fbe
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Inline Side-by-side
Showing with 53 additions and 58 deletions
drivers/net/ethernet/mediatek/mtk_eth_soc.c
View file @ 14a44ab0
......@@ -263,6 +263,25 @@ static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
mtk_w32(eth, val, TRGMII_TCK_CTRL);
}
static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
phy_interface_t interface)
{
struct mtk_mac *mac = container_of(config, struct mtk_mac,
phylink_config);
struct mtk_eth *eth = mac->hw;
unsigned int sid;
if (interface == PHY_INTERFACE_MODE_SGMII ||
phy_interface_mode_is_8023z(interface)) {
sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
0 : mac->id;
return mtk_sgmii_select_pcs(eth->sgmii, sid);
}
return NULL;
}
static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
const struct phylink_link_state *state)
{
......@@ -270,7 +289,7 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
phylink_config);
struct mtk_eth *eth = mac->hw;
int val, ge_mode, err = 0;
u32 sid, i;
u32 i;
/* MT76x8 has no hardware settings between for the MAC */
if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
......@@ -391,15 +410,6 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
SYSCFG0_SGMII_MASK,
~(u32)SYSCFG0_SGMII_MASK);
/* Decide how GMAC and SGMIISYS be mapped */
sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
0 : mac->id;
/* Setup SGMIISYS with the determined property */
err = mtk_sgmii_config(eth->sgmii, sid, mode, state->interface);
if (err)
goto init_err;
/* Save the syscfg0 value for mac_finish */
mac->syscfg0 = val;
} else if (phylink_autoneg_inband(mode)) {
......@@ -479,14 +489,6 @@ static void mtk_mac_pcs_get_state(struct phylink_config *config,
state->pause |= MLO_PAUSE_TX;
}
static void mtk_mac_an_restart(struct phylink_config *config)
{
struct mtk_mac *mac = container_of(config, struct mtk_mac,
phylink_config);
mtk_sgmii_restart_an(mac->hw, mac->id);
}
static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
phy_interface_t interface)
{
......@@ -507,15 +509,6 @@ static void mtk_mac_link_up(struct phylink_config *config,
phylink_config);
u32 mcr;
if (phy_interface_mode_is_8023z(interface)) {
struct mtk_eth *eth = mac->hw;
/* Decide how GMAC and SGMIISYS be mapped */
int sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
0 : mac->id;
mtk_sgmii_link_up(eth->sgmii, sid, speed, duplex);
}
mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
......@@ -548,8 +541,8 @@ static void mtk_mac_link_up(struct phylink_config *config,
static const struct phylink_mac_ops mtk_phylink_ops = {
.validate = phylink_generic_validate,
.mac_select_pcs = mtk_mac_select_pcs,
.mac_pcs_get_state = mtk_mac_pcs_get_state,
.mac_an_restart = mtk_mac_an_restart,
.mac_config = mtk_mac_config,
.mac_finish = mtk_mac_finish,
.mac_link_down = mtk_mac_link_down,
......
drivers/net/ethernet/mediatek/mtk_eth_soc.h
View file @ 14a44ab0
......@@ -874,10 +874,12 @@ struct mtk_soc_data {
* @regmap: The register map pointing at the range used to setup
* SGMII modes
* @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
* @pcs: Phylink PCS structure
*/
struct mtk_pcs {
struct regmap *regmap;
u32 ana_rgc3;
struct phylink_pcs pcs;
};
/* struct mtk_sgmii - This is the structure holding sgmii regmap and its
......@@ -1020,12 +1022,9 @@ void mtk_stats_update_mac(struct mtk_mac *mac);
void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id);
int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
u32 ana_rgc3);
int mtk_sgmii_config(struct mtk_sgmii *ss, int id, unsigned int mode,
phy_interface_t interface);
void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex);
void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id);
int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
......
drivers/net/ethernet/mediatek/mtk_sgmii.c
View file @ 14a44ab0
......@@ -14,14 +14,16 @@
#include "mtk_eth_soc.h"
static struct mtk_pcs *pcs_to_mtk_pcs(struct phylink_pcs *pcs)
{
return container_of(pcs, struct mtk_pcs, pcs);
}
/* For SGMII interface mode */
static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
{
unsigned int val;
if (!mpcs->regmap)
return -EINVAL;
/* Setup the link timer and QPHY power up inside SGMIISYS */
regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
SGMII_LINK_TIMER_DEFAULT);
......@@ -50,9 +52,6 @@ static int mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs,
{
unsigned int val;
if (!mpcs->regmap)
return -EINVAL;
regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
val &= ~RG_PHY_SPEED_MASK;
if (interface == PHY_INTERFACE_MODE_2500BASEX)
......@@ -78,10 +77,12 @@ static int mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs,
return 0;
}
int mtk_sgmii_config(struct mtk_sgmii *ss, int id, unsigned int mode,
phy_interface_t interface)
static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
phy_interface_t interface,
const unsigned long *advertising,
bool permit_pause_to_mac)
{
struct mtk_pcs *mpcs = &ss->pcs[id];
struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
int err = 0;
/* Setup SGMIISYS with the determined property */
......@@ -93,22 +94,25 @@ int mtk_sgmii_config(struct mtk_sgmii *ss, int id, unsigned int mode,
return err;
}
static void mtk_pcs_restart_an(struct mtk_pcs *mpcs)
static void mtk_pcs_restart_an(struct phylink_pcs *pcs)
{
struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
unsigned int val;
if (!mpcs->regmap)
return;
regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
val |= SGMII_AN_RESTART;
regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
}
static void mtk_pcs_link_up(struct mtk_pcs *mpcs, int speed, int duplex)
static void mtk_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
phy_interface_t interface, int speed, int duplex)
{
struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
unsigned int val;
if (!phy_interface_mode_is_8023z(interface))
return;
/* SGMII force duplex setting */
regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
val &= ~SGMII_DUPLEX_FULL;
......@@ -118,11 +122,11 @@ static void mtk_pcs_link_up(struct mtk_pcs *mpcs, int speed, int duplex)
regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
}
/* For 1000BASE-X and 2500BASE-X interface modes */
void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex)
{
mtk_pcs_link_up(&ss->pcs[id], speed, duplex);
}
static const struct phylink_pcs_ops mtk_pcs_ops = {
.pcs_config = mtk_pcs_config,
.pcs_an_restart = mtk_pcs_restart_an,
.pcs_link_up = mtk_pcs_link_up,
};
int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
{
......@@ -139,18 +143,17 @@ int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
of_node_put(np);
if (IS_ERR(ss->pcs[i].regmap))
return PTR_ERR(ss->pcs[i].regmap);
ss->pcs[i].pcs.ops = &mtk_pcs_ops;
}
return 0;
}
void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id)
struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id)
{
unsigned int sid;
/* Decide how GMAC and SGMIISYS be mapped */
sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
0 : mac_id;
if (!ss->pcs[id].regmap)
return NULL;
mtk_pcs_restart_an(&eth->sgmii->pcs[sid]);
return &ss->pcs[id].pcs;
}
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