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Commit 151bd6c5 authored by Markus Schneider-Pargmann's avatar Markus Schneider-Pargmann Committed by Ulf Hansson
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pmdomain: mediatek: Unify configuration for infracfg and smi 

Use flags to distinguish between infracfg and smi subsystem for a bus
protection configuration. It simplifies enabling/disabling and prepares
the driver for the use of another regmap for mt8365.
Signed-off-by: default avatarMarkus Schneider-Pargmann <msp@baylibre.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarAlexandre Mergnat <amergnat@baylibre.com>
Tested-by: default avatarAlexandre Mergnat <amergnat@baylibre.com>
Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.comSigned-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 2ec81379
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Showing with 612 additions and 425 deletions
drivers/pmdomain/mediatek/mt6795-pm-domains.h
View file @ 151bd6c5
...@@ -46,9 +46,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt6795[] = { ...@@ -46,9 +46,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt6795[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8), .sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
MT8173_TOP_AXI_PROT_EN_MM_M1), MT8173_TOP_AXI_PROT_EN_MM_M1),
}, },
}, },
[MT6795_POWER_DOMAIN_MJC] = { [MT6795_POWER_DOMAIN_MJC] = {
...@@ -95,11 +95,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt6795[] = { ...@@ -95,11 +95,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt6795[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(13, 8), .sram_pdn_bits = GENMASK(13, 8),
.sram_pdn_ack_bits = GENMASK(21, 16), .sram_pdn_ack_bits = GENMASK(21, 16),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
MT8173_TOP_AXI_PROT_EN_MFG_M0 | MT8173_TOP_AXI_PROT_EN_MFG_M0 |
MT8173_TOP_AXI_PROT_EN_MFG_M1 | MT8173_TOP_AXI_PROT_EN_MFG_M1 |
MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
}, },
}, },
}; };
......
drivers/pmdomain/mediatek/mt8167-pm-domains.h
View file @ 151bd6c5
...@@ -22,9 +22,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { ...@@ -22,9 +22,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8), .sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI | BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |
MT8167_TOP_AXI_PROT_EN_MCU_MM), MT8167_TOP_AXI_PROT_EN_MCU_MM),
}, },
.caps = MTK_SCPD_ACTIVE_WAKEUP, .caps = MTK_SCPD_ACTIVE_WAKEUP,
}, },
...@@ -56,9 +56,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { ...@@ -56,9 +56,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = 0, .sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0, .sram_pdn_ack_bits = 0,
.bp_infracfg = { .bp_cfg = {
BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG | BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |
MT8167_TOP_AXI_PROT_EN_MFG_EMI), MT8167_TOP_AXI_PROT_EN_MFG_EMI),
}, },
}, },
[MT8167_POWER_DOMAIN_MFG_2D] = { [MT8167_POWER_DOMAIN_MFG_2D] = {
...@@ -88,10 +88,10 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { ...@@ -88,10 +88,10 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = 0, .sram_pdn_ack_bits = 0,
.caps = MTK_SCPD_ACTIVE_WAKEUP, .caps = MTK_SCPD_ACTIVE_WAKEUP,
.bp_infracfg = { .bp_cfg = {
BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI | BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |
MT8167_TOP_AXI_PROT_EN_CONN_MCU | MT8167_TOP_AXI_PROT_EN_CONN_MCU |
MT8167_TOP_AXI_PROT_EN_MCU_CONN), MT8167_TOP_AXI_PROT_EN_MCU_CONN),
}, },
}, },
}; };
......
drivers/pmdomain/mediatek/mt8173-pm-domains.h
View file @ 151bd6c5
...@@ -46,9 +46,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { ...@@ -46,9 +46,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8), .sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
MT8173_TOP_AXI_PROT_EN_MM_M1), MT8173_TOP_AXI_PROT_EN_MM_M1),
}, },
}, },
[MT8173_POWER_DOMAIN_VENC_LT] = { [MT8173_POWER_DOMAIN_VENC_LT] = {
...@@ -106,11 +106,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { ...@@ -106,11 +106,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(13, 8), .sram_pdn_bits = GENMASK(13, 8),
.sram_pdn_ack_bits = GENMASK(21, 16), .sram_pdn_ack_bits = GENMASK(21, 16),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
MT8173_TOP_AXI_PROT_EN_MFG_M0 | MT8173_TOP_AXI_PROT_EN_MFG_M0 |
MT8173_TOP_AXI_PROT_EN_MFG_M1 | MT8173_TOP_AXI_PROT_EN_MFG_M1 |
MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
}, },
}, },
}; };
......
drivers/pmdomain/mediatek/mt8183-pm-domains.h
View file @ 151bd6c5
...@@ -28,9 +28,12 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { ...@@ -28,9 +28,12 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184, .pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = 0, .sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0, .sram_pdn_ack_bits = 0,
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET, BUS_PROT_WR(INFRA,
MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), MT8183_TOP_AXI_PROT_EN_CONN,
MT8183_TOP_AXI_PROT_EN_SET,
MT8183_TOP_AXI_PROT_EN_CLR,
MT8183_TOP_AXI_PROT_EN_STA1),
}, },
}, },
[MT8183_POWER_DOMAIN_MFG_ASYNC] = { [MT8183_POWER_DOMAIN_MFG_ASYNC] = {
...@@ -79,11 +82,17 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { ...@@ -79,11 +82,17 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184, .pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET, BUS_PROT_WR(INFRA,
MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), MT8183_TOP_AXI_PROT_EN_1_MFG,
BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET, MT8183_TOP_AXI_PROT_EN_1_SET,
MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), MT8183_TOP_AXI_PROT_EN_1_CLR,
MT8183_TOP_AXI_PROT_EN_STA1_1),
BUS_PROT_WR(INFRA,
MT8183_TOP_AXI_PROT_EN_MFG,
MT8183_TOP_AXI_PROT_EN_SET,
MT8183_TOP_AXI_PROT_EN_CLR,
MT8183_TOP_AXI_PROT_EN_STA1),
}, },
}, },
[MT8183_POWER_DOMAIN_DISP] = { [MT8183_POWER_DOMAIN_DISP] = {
...@@ -94,14 +103,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { ...@@ -94,14 +103,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184, .pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET, BUS_PROT_WR(INFRA,
MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), MT8183_TOP_AXI_PROT_EN_1_DISP,
BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET, MT8183_TOP_AXI_PROT_EN_1_SET,
MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), MT8183_TOP_AXI_PROT_EN_1_CLR,
}, MT8183_TOP_AXI_PROT_EN_STA1_1),
.bp_smi = { BUS_PROT_WR(INFRA,
BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP, MT8183_TOP_AXI_PROT_EN_DISP,
MT8183_TOP_AXI_PROT_EN_SET,
MT8183_TOP_AXI_PROT_EN_CLR,
MT8183_TOP_AXI_PROT_EN_STA1),
BUS_PROT_WR(SMI,
MT8183_SMI_COMMON_SMI_CLAMP_DISP,
MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_SET,
MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN_CLR,
MT8183_SMI_COMMON_CLAMP_EN), MT8183_SMI_COMMON_CLAMP_EN),
...@@ -115,18 +129,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { ...@@ -115,18 +129,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184, .pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(9, 8), .sram_pdn_bits = GENMASK(9, 8),
.sram_pdn_ack_bits = GENMASK(13, 12), .sram_pdn_ack_bits = GENMASK(13, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SET, BUS_PROT_WR(INFRA,
MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), MT8183_TOP_AXI_PROT_EN_MM_CAM,
BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET, MT8183_TOP_AXI_PROT_EN_MM_SET,
MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), MT8183_TOP_AXI_PROT_EN_MM_CLR,
BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND, MT8183_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(INFRA,
MT8183_TOP_AXI_PROT_EN_CAM,
MT8183_TOP_AXI_PROT_EN_SET,
MT8183_TOP_AXI_PROT_EN_CLR,
MT8183_TOP_AXI_PROT_EN_STA1),
BUS_PROT_WR_IGN(INFRA,
MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND,
MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_SET,
MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_CLR,
MT8183_TOP_AXI_PROT_EN_MM_STA1), MT8183_TOP_AXI_PROT_EN_MM_STA1),
}, BUS_PROT_WR(SMI,
.bp_smi = { MT8183_SMI_COMMON_SMI_CLAMP_CAM,
BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM,
MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_SET,
MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN_CLR,
MT8183_SMI_COMMON_CLAMP_EN), MT8183_SMI_COMMON_CLAMP_EN),
...@@ -140,18 +160,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { ...@@ -140,18 +160,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184, .pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(9, 8), .sram_pdn_bits = GENMASK(9, 8),
.sram_pdn_ack_bits = GENMASK(13, 12), .sram_pdn_ack_bits = GENMASK(13, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP, BUS_PROT_WR(INFRA,
MT8183_TOP_AXI_PROT_EN_MM_ISP,
MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_SET,
MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_CLR,
MT8183_TOP_AXI_PROT_EN_MM_STA1), MT8183_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND, BUS_PROT_WR_IGN(INFRA,
MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND,
MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_SET,
MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_CLR,
MT8183_TOP_AXI_PROT_EN_MM_STA1), MT8183_TOP_AXI_PROT_EN_MM_STA1),
}, BUS_PROT_WR(SMI,
.bp_smi = { MT8183_SMI_COMMON_SMI_CLAMP_ISP,
BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP,
MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_SET,
MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN_CLR,
MT8183_SMI_COMMON_CLAMP_EN), MT8183_SMI_COMMON_CLAMP_EN),
...@@ -165,8 +186,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { ...@@ -165,8 +186,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184, .pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_smi = { .bp_cfg = {
BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC, BUS_PROT_WR(SMI,
MT8183_SMI_COMMON_SMI_CLAMP_VDEC,
MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_SET,
MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN_CLR,
MT8183_SMI_COMMON_CLAMP_EN), MT8183_SMI_COMMON_CLAMP_EN),
...@@ -180,8 +202,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { ...@@ -180,8 +202,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184, .pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(11, 8), .sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12), .sram_pdn_ack_bits = GENMASK(15, 12),
.bp_smi = { .bp_cfg = {
BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC, BUS_PROT_WR(SMI,
MT8183_SMI_COMMON_SMI_CLAMP_VENC,
MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_SET,
MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN_CLR,
MT8183_SMI_COMMON_CLAMP_EN), MT8183_SMI_COMMON_CLAMP_EN),
...@@ -195,22 +218,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { ...@@ -195,22 +218,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184, .pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP, BUS_PROT_WR(INFRA,
MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP,
MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_SET,
MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_CLR,
MT8183_TOP_AXI_PROT_EN_MM_STA1), MT8183_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP, BUS_PROT_WR(INFRA,
MT8183_TOP_AXI_PROT_EN_VPU_TOP,
MT8183_TOP_AXI_PROT_EN_SET, MT8183_TOP_AXI_PROT_EN_SET,
MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_CLR,
MT8183_TOP_AXI_PROT_EN_STA1), MT8183_TOP_AXI_PROT_EN_STA1),
BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND, BUS_PROT_WR(INFRA,
MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND,
MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_SET,
MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_CLR,
MT8183_TOP_AXI_PROT_EN_MM_STA1), MT8183_TOP_AXI_PROT_EN_MM_STA1),
}, BUS_PROT_WR(SMI,
.bp_smi = { MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP,
BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP,
MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_SET,
MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN_CLR,
MT8183_SMI_COMMON_CLAMP_EN), MT8183_SMI_COMMON_CLAMP_EN),
...@@ -224,12 +249,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { ...@@ -224,12 +249,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184, .pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(11, 8), .sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12), .sram_pdn_ack_bits = GENMASK(13, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0, BUS_PROT_WR(INFRA,
MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0,
MT8183_TOP_AXI_PROT_EN_MCU_SET, MT8183_TOP_AXI_PROT_EN_MCU_SET,
MT8183_TOP_AXI_PROT_EN_MCU_CLR, MT8183_TOP_AXI_PROT_EN_MCU_CLR,
MT8183_TOP_AXI_PROT_EN_MCU_STA1), MT8183_TOP_AXI_PROT_EN_MCU_STA1),
BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND, BUS_PROT_WR(INFRA,
MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND,
MT8183_TOP_AXI_PROT_EN_MCU_SET, MT8183_TOP_AXI_PROT_EN_MCU_SET,
MT8183_TOP_AXI_PROT_EN_MCU_CLR, MT8183_TOP_AXI_PROT_EN_MCU_CLR,
MT8183_TOP_AXI_PROT_EN_MCU_STA1), MT8183_TOP_AXI_PROT_EN_MCU_STA1),
...@@ -244,12 +271,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { ...@@ -244,12 +271,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184, .pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(11, 8), .sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12), .sram_pdn_ack_bits = GENMASK(13, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1, BUS_PROT_WR(INFRA,
MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1,
MT8183_TOP_AXI_PROT_EN_MCU_SET, MT8183_TOP_AXI_PROT_EN_MCU_SET,
MT8183_TOP_AXI_PROT_EN_MCU_CLR, MT8183_TOP_AXI_PROT_EN_MCU_CLR,
MT8183_TOP_AXI_PROT_EN_MCU_STA1), MT8183_TOP_AXI_PROT_EN_MCU_STA1),
BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND, BUS_PROT_WR(INFRA,
MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND,
MT8183_TOP_AXI_PROT_EN_MCU_SET, MT8183_TOP_AXI_PROT_EN_MCU_SET,
MT8183_TOP_AXI_PROT_EN_MCU_CLR, MT8183_TOP_AXI_PROT_EN_MCU_CLR,
MT8183_TOP_AXI_PROT_EN_MCU_STA1), MT8183_TOP_AXI_PROT_EN_MCU_STA1),
......
drivers/pmdomain/mediatek/mt8192-pm-domains.h
View file @ 151bd6c5
...@@ -19,8 +19,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { ...@@ -19,8 +19,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170, .pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_2_AUDIO,
MT8192_TOP_AXI_PROT_EN_2_SET, MT8192_TOP_AXI_PROT_EN_2_SET,
MT8192_TOP_AXI_PROT_EN_2_CLR, MT8192_TOP_AXI_PROT_EN_2_CLR,
MT8192_TOP_AXI_PROT_EN_2_STA1), MT8192_TOP_AXI_PROT_EN_2_STA1),
...@@ -34,16 +35,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { ...@@ -34,16 +35,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170, .pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = 0, .sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0, .sram_pdn_ack_bits = 0,
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_CONN,
MT8192_TOP_AXI_PROT_EN_SET, MT8192_TOP_AXI_PROT_EN_SET,
MT8192_TOP_AXI_PROT_EN_CLR, MT8192_TOP_AXI_PROT_EN_CLR,
MT8192_TOP_AXI_PROT_EN_STA1), MT8192_TOP_AXI_PROT_EN_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_CONN_2ND,
MT8192_TOP_AXI_PROT_EN_SET, MT8192_TOP_AXI_PROT_EN_SET,
MT8192_TOP_AXI_PROT_EN_CLR, MT8192_TOP_AXI_PROT_EN_CLR,
MT8192_TOP_AXI_PROT_EN_STA1), MT8192_TOP_AXI_PROT_EN_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_1_CONN,
MT8192_TOP_AXI_PROT_EN_1_SET, MT8192_TOP_AXI_PROT_EN_1_SET,
MT8192_TOP_AXI_PROT_EN_1_CLR, MT8192_TOP_AXI_PROT_EN_1_CLR,
MT8192_TOP_AXI_PROT_EN_1_STA1), MT8192_TOP_AXI_PROT_EN_1_STA1),
...@@ -68,20 +72,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { ...@@ -68,20 +72,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170, .pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_1_MFG1,
MT8192_TOP_AXI_PROT_EN_1_SET, MT8192_TOP_AXI_PROT_EN_1_SET,
MT8192_TOP_AXI_PROT_EN_1_CLR, MT8192_TOP_AXI_PROT_EN_1_CLR,
MT8192_TOP_AXI_PROT_EN_1_STA1), MT8192_TOP_AXI_PROT_EN_1_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_2_MFG1,
MT8192_TOP_AXI_PROT_EN_2_SET, MT8192_TOP_AXI_PROT_EN_2_SET,
MT8192_TOP_AXI_PROT_EN_2_CLR, MT8192_TOP_AXI_PROT_EN_2_CLR,
MT8192_TOP_AXI_PROT_EN_2_STA1), MT8192_TOP_AXI_PROT_EN_2_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MFG1,
MT8192_TOP_AXI_PROT_EN_SET, MT8192_TOP_AXI_PROT_EN_SET,
MT8192_TOP_AXI_PROT_EN_CLR, MT8192_TOP_AXI_PROT_EN_CLR,
MT8192_TOP_AXI_PROT_EN_STA1), MT8192_TOP_AXI_PROT_EN_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND,
MT8192_TOP_AXI_PROT_EN_2_SET, MT8192_TOP_AXI_PROT_EN_2_SET,
MT8192_TOP_AXI_PROT_EN_2_CLR, MT8192_TOP_AXI_PROT_EN_2_CLR,
MT8192_TOP_AXI_PROT_EN_2_STA1), MT8192_TOP_AXI_PROT_EN_2_STA1),
...@@ -141,24 +149,29 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { ...@@ -141,24 +149,29 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170, .pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP, BUS_PROT_WR_IGN(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_DISP,
MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_SET,
MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_CLR,
MT8192_TOP_AXI_PROT_EN_MM_STA1), MT8192_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP, BUS_PROT_WR_IGN(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_2_DISP,
MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_SET,
MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
MT8192_TOP_AXI_PROT_EN_MM_2_STA1), MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_DISP, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_DISP,
MT8192_TOP_AXI_PROT_EN_SET, MT8192_TOP_AXI_PROT_EN_SET,
MT8192_TOP_AXI_PROT_EN_CLR, MT8192_TOP_AXI_PROT_EN_CLR,
MT8192_TOP_AXI_PROT_EN_STA1), MT8192_TOP_AXI_PROT_EN_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND,
MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_SET,
MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_CLR,
MT8192_TOP_AXI_PROT_EN_MM_STA1), MT8192_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND,
MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_SET,
MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
MT8192_TOP_AXI_PROT_EN_MM_2_STA1), MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
...@@ -172,12 +185,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { ...@@ -172,12 +185,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170, .pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_IPE,
MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_SET,
MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_CLR,
MT8192_TOP_AXI_PROT_EN_MM_STA1), MT8192_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND,
MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_SET,
MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_CLR,
MT8192_TOP_AXI_PROT_EN_MM_STA1), MT8192_TOP_AXI_PROT_EN_MM_STA1),
...@@ -191,12 +206,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { ...@@ -191,12 +206,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170, .pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_2_ISP,
MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_SET,
MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
MT8192_TOP_AXI_PROT_EN_MM_2_STA1), MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND,
MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_SET,
MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
MT8192_TOP_AXI_PROT_EN_MM_2_STA1), MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
...@@ -210,12 +227,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { ...@@ -210,12 +227,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170, .pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_ISP2,
MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_SET,
MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_CLR,
MT8192_TOP_AXI_PROT_EN_MM_STA1), MT8192_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND,
MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_SET,
MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_CLR,
MT8192_TOP_AXI_PROT_EN_MM_STA1), MT8192_TOP_AXI_PROT_EN_MM_STA1),
...@@ -229,12 +248,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { ...@@ -229,12 +248,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170, .pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_2_MDP,
MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_SET,
MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
MT8192_TOP_AXI_PROT_EN_MM_2_STA1), MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND,
MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_SET,
MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
MT8192_TOP_AXI_PROT_EN_MM_2_STA1), MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
...@@ -248,12 +269,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { ...@@ -248,12 +269,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170, .pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_VENC,
MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_SET,
MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_CLR,
MT8192_TOP_AXI_PROT_EN_MM_STA1), MT8192_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND,
MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_SET,
MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_CLR,
MT8192_TOP_AXI_PROT_EN_MM_STA1), MT8192_TOP_AXI_PROT_EN_MM_STA1),
...@@ -267,12 +290,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { ...@@ -267,12 +290,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170, .pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_VDEC,
MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_SET,
MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_CLR,
MT8192_TOP_AXI_PROT_EN_MM_STA1), MT8192_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND,
MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_SET,
MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_CLR,
MT8192_TOP_AXI_PROT_EN_MM_STA1), MT8192_TOP_AXI_PROT_EN_MM_STA1),
...@@ -295,24 +320,29 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { ...@@ -295,24 +320,29 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170, .pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12), .sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = { .bp_cfg = {
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_CAM, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_2_CAM,
MT8192_TOP_AXI_PROT_EN_2_SET, MT8192_TOP_AXI_PROT_EN_2_SET,
MT8192_TOP_AXI_PROT_EN_2_CLR, MT8192_TOP_AXI_PROT_EN_2_CLR,
MT8192_TOP_AXI_PROT_EN_2_STA1), MT8192_TOP_AXI_PROT_EN_2_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_CAM,
MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_SET,
MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_CLR,
MT8192_TOP_AXI_PROT_EN_MM_STA1), MT8192_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CAM, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_1_CAM,
MT8192_TOP_AXI_PROT_EN_1_SET, MT8192_TOP_AXI_PROT_EN_1_SET,
MT8192_TOP_AXI_PROT_EN_1_CLR, MT8192_TOP_AXI_PROT_EN_1_CLR,
MT8192_TOP_AXI_PROT_EN_1_STA1), MT8192_TOP_AXI_PROT_EN_1_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND,
MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_SET,
MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_CLR,
MT8192_TOP_AXI_PROT_EN_MM_STA1), MT8192_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM, BUS_PROT_WR(INFRA,
MT8192_TOP_AXI_PROT_EN_VDNR_CAM,
MT8192_TOP_AXI_PROT_EN_VDNR_SET, MT8192_TOP_AXI_PROT_EN_VDNR_SET,
MT8192_TOP_AXI_PROT_EN_VDNR_CLR, MT8192_TOP_AXI_PROT_EN_VDNR_CLR,
MT8192_TOP_AXI_PROT_EN_VDNR_STA1), MT8192_TOP_AXI_PROT_EN_VDNR_STA1),
......
drivers/pmdomain/mediatek/mtk-pm-domains.c
View file @ 151bd6c5
...@@ -118,9 +118,19 @@ static int scpsys_sram_disable(struct scpsys_domain *pd) ...@@ -118,9 +118,19 @@ static int scpsys_sram_disable(struct scpsys_domain *pd)
MTK_POLL_TIMEOUT); MTK_POLL_TIMEOUT);
} }
static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd, static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *pd,
struct regmap *regmap) const struct scpsys_bus_prot_data *bpd)
{ {
if (bpd->flags & BUS_PROT_COMPONENT_SMI)
return pd->smi;
else
return pd->infracfg;
}
static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
const struct scpsys_bus_prot_data *bpd)
{
struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
u32 sta_mask = bpd->bus_prot_sta_mask; u32 sta_mask = bpd->bus_prot_sta_mask;
u32 val; u32 val;
...@@ -137,9 +147,10 @@ static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd, ...@@ -137,9 +147,10 @@ static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd,
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
} }
static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd, static int scpsys_bus_protect_set(struct scpsys_domain *pd,
struct regmap *regmap) const struct scpsys_bus_prot_data *bpd)
{ {
struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
u32 sta_mask = bpd->bus_prot_sta_mask; u32 sta_mask = bpd->bus_prot_sta_mask;
u32 val; u32 val;
...@@ -153,15 +164,16 @@ static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd, ...@@ -153,15 +164,16 @@ static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd,
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
} }
static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, struct regmap *regmap) static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
{ {
int i, ret; for (int i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) {
const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i];
int ret;
for (i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) { if (!bpd->bus_prot_set_clr_mask)
if (!bpd[i].bus_prot_set_clr_mask)
break; break;
ret = scpsys_bus_protect_set(&bpd[i], regmap); ret = scpsys_bus_protect_set(pd, bpd);
if (ret) if (ret)
return ret; return ret;
} }
...@@ -169,27 +181,16 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st ...@@ -169,27 +181,16 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st
return 0; return 0;
} }
static int scpsys_bus_protect_enable(struct scpsys_domain *pd) static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
{
int ret;
ret = _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg);
if (ret)
return ret;
return _scpsys_bus_protect_enable(pd->data->bp_smi, pd->smi);
}
static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
struct regmap *regmap)
{ {
int i, ret; for (int i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) {
const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i];
int ret;
for (i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) { if (!bpd->bus_prot_set_clr_mask)
if (!bpd[i].bus_prot_set_clr_mask)
continue; continue;
ret = scpsys_bus_protect_clear(&bpd[i], regmap); ret = scpsys_bus_protect_clear(pd, bpd);
if (ret) if (ret)
return ret; return ret;
} }
...@@ -197,17 +198,6 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd, ...@@ -197,17 +198,6 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
return 0; return 0;
} }
static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
{
int ret;
ret = _scpsys_bus_protect_disable(pd->data->bp_smi, pd->smi);
if (ret)
return ret;
return _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg);
}
static int scpsys_regulator_enable(struct regulator *supply) static int scpsys_regulator_enable(struct regulator *supply)
{ {
return supply ? regulator_enable(supply) : 0; return supply ? regulator_enable(supply) : 0;
......
drivers/pmdomain/mediatek/mtk-pm-domains.h
View file @ 151bd6c5
...@@ -45,6 +45,8 @@ ...@@ -45,6 +45,8 @@
enum scpsys_bus_prot_flags { enum scpsys_bus_prot_flags {
BUS_PROT_REG_UPDATE = BIT(1), BUS_PROT_REG_UPDATE = BIT(1),
BUS_PROT_IGNORE_CLR_ACK = BIT(2), BUS_PROT_IGNORE_CLR_ACK = BIT(2),
BUS_PROT_COMPONENT_INFRA = BIT(4),
BUS_PROT_COMPONENT_SMI = BIT(5),
}; };
#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \ #define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \
...@@ -56,17 +58,19 @@ enum scpsys_bus_prot_flags { ...@@ -56,17 +58,19 @@ enum scpsys_bus_prot_flags {
.flags = _flags \ .flags = _flags \
} }
#define BUS_PROT_WR(_mask, _set, _clr, _sta) \ #define BUS_PROT_WR(_hwip, _mask, _set, _clr, _sta) \
_BUS_PROT(_mask, _set, _clr, _mask, _sta, 0) _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_##_hwip)
#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ #define BUS_PROT_WR_IGN(_hwip, _mask, _set, _clr, _sta) \
_BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_IGNORE_CLR_ACK) _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
BUS_PROT_COMPONENT_##_hwip | BUS_PROT_IGNORE_CLR_ACK)
#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ #define BUS_PROT_UPDATE(_hwip, _mask, _set, _clr, _sta) \
_BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_REG_UPDATE) _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
BUS_PROT_COMPONENT_##_hwip | BUS_PROT_REG_UPDATE)
#define BUS_PROT_UPDATE_TOPAXI(_mask) \ #define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \
BUS_PROT_UPDATE(_mask, \ BUS_PROT_UPDATE(INFRA, _mask, \
INFRA_TOPAXI_PROTECTEN, \ INFRA_TOPAXI_PROTECTEN, \
INFRA_TOPAXI_PROTECTEN, \ INFRA_TOPAXI_PROTECTEN, \
INFRA_TOPAXI_PROTECTSTA1) INFRA_TOPAXI_PROTECTSTA1)
...@@ -90,8 +94,7 @@ struct scpsys_bus_prot_data { ...@@ -90,8 +94,7 @@ struct scpsys_bus_prot_data {
* @ext_buck_iso_offs: The offset for external buck isolation * @ext_buck_iso_offs: The offset for external buck isolation
* @ext_buck_iso_mask: The mask for external buck isolation * @ext_buck_iso_mask: The mask for external buck isolation
* @caps: The flag for active wake-up action. * @caps: The flag for active wake-up action.
* @bp_infracfg: bus protection for infracfg subsystem * @bp_cfg: bus protection configuration for any subsystem
* @bp_smi: bus protection for smi subsystem
*/ */
struct scpsys_domain_data { struct scpsys_domain_data {
const char *name; const char *name;
...@@ -102,8 +105,7 @@ struct scpsys_domain_data { ...@@ -102,8 +105,7 @@ struct scpsys_domain_data {
int ext_buck_iso_offs; int ext_buck_iso_offs;
u32 ext_buck_iso_mask; u32 ext_buck_iso_mask;
u8 caps; u8 caps;
const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA]; const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA];
const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA];
int pwr_sta_offs; int pwr_sta_offs;
int pwr_sta2nd_offs; int pwr_sta2nd_offs;
}; };
......
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