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Commit 1582e1d1 authored by Sumit Gupta's avatar Sumit Gupta Committed by Thierry Reding
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arm64: tegra: Add CPU OPP tables and interconnects property 

Add OPP table and interconnects property to scale DDR frequency with
CPU frequency for better performance. Each operating point entry of
the OPP table has CPU freq to per MC channel bandwidth mapping.
One table is added for each cluster even though the table data is
same because the bandwidth request is per cluster. This is done
because OPP framework creates a single icc path and hence single
bandwidth request if the table is marked as 'opp-shared' and shared
among all clusters. For us, the OPP table data is same but the MC
Client ID argument to interconnects property is different for each
cluster. So, having per cluster table makes different icc path for
each cluster and helps to make per cluster BW requests.
Signed-off-by: default avatarSumit Gupta <sumitg@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent c95711d7
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arch/arm64/boot/dts/nvidia/tegra234.dtsi
View file @ 1582e1d1
......@@ -3028,6 +3028,9 @@ cpu0_0: cpu@0 {
enable-method = "psci";
operating-points-v2 = <&cl0_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
......@@ -3044,6 +3047,9 @@ cpu0_1: cpu@100 {
enable-method = "psci";
operating-points-v2 = <&cl0_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
......@@ -3060,6 +3066,9 @@ cpu0_2: cpu@200 {
enable-method = "psci";
operating-points-v2 = <&cl0_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
......@@ -3076,6 +3085,9 @@ cpu0_3: cpu@300 {
enable-method = "psci";
operating-points-v2 = <&cl0_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
......@@ -3092,6 +3104,9 @@ cpu1_0: cpu@10000 {
enable-method = "psci";
operating-points-v2 = <&cl1_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
......@@ -3108,6 +3123,9 @@ cpu1_1: cpu@10100 {
enable-method = "psci";
operating-points-v2 = <&cl1_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
......@@ -3124,6 +3142,9 @@ cpu1_2: cpu@10200 {
enable-method = "psci";
operating-points-v2 = <&cl1_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
......@@ -3140,6 +3161,9 @@ cpu1_3: cpu@10300 {
enable-method = "psci";
operating-points-v2 = <&cl1_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
......@@ -3156,6 +3180,9 @@ cpu2_0: cpu@20000 {
enable-method = "psci";
operating-points-v2 = <&cl2_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
......@@ -3172,6 +3199,9 @@ cpu2_1: cpu@20100 {
enable-method = "psci";
operating-points-v2 = <&cl2_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
......@@ -3188,6 +3218,9 @@ cpu2_2: cpu@20200 {
enable-method = "psci";
operating-points-v2 = <&cl2_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
......@@ -3204,6 +3237,9 @@ cpu2_3: cpu@20300 {
enable-method = "psci";
operating-points-v2 = <&cl2_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
......@@ -3478,4 +3514,244 @@ timer {
interrupt-parent = <&gic>;
always-on;
};
cl0_opp_tbl: opp-table-cluster0 {
compatible = "operating-points-v2";
opp-shared;
cl0_ch1_opp1: opp-115200000 {
opp-hz = /bits/ 64 <115200000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp2: opp-268800000 {
opp-hz = /bits/ 64 <268800000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp3: opp-422400000 {
opp-hz = /bits/ 64 <422400000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp4: opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp5: opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp6: opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp7: opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp8: opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp9: opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <1632000>;
};
cl0_ch1_opp10: opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <1632000>;
};
cl0_ch1_opp11: opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-peak-kBps = <2660000>;
};
cl0_ch1_opp12: opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <2660000>;
};
cl0_ch1_opp13: opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <3200000>;
};
cl0_ch1_opp14: opp-2112000000 {
opp-hz = /bits/ 64 <2112000000>;
opp-peak-kBps = <6400000>;
};
cl0_ch1_opp15: opp-2201600000 {
opp-hz = /bits/ 64 <2201600000>;
opp-peak-kBps = <6400000>;
};
};
cl1_opp_tbl: opp-table-cluster1 {
compatible = "operating-points-v2";
opp-shared;
cl1_ch1_opp1: opp-115200000 {
opp-hz = /bits/ 64 <115200000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp2: opp-268800000 {
opp-hz = /bits/ 64 <268800000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp3: opp-422400000 {
opp-hz = /bits/ 64 <422400000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp4: opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp5: opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp6: opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp7: opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp8: opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp9: opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <1632000>;
};
cl1_ch1_opp10: opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <1632000>;
};
cl1_ch1_opp11: opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-peak-kBps = <2660000>;
};
cl1_ch1_opp12: opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <2660000>;
};
cl1_ch1_opp13: opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <3200000>;
};
cl1_ch1_opp14: opp-2112000000 {
opp-hz = /bits/ 64 <2112000000>;
opp-peak-kBps = <6400000>;
};
cl1_ch1_opp15: opp-2201600000 {
opp-hz = /bits/ 64 <2201600000>;
opp-peak-kBps = <6400000>;
};
};
cl2_opp_tbl: opp-table-cluster2 {
compatible = "operating-points-v2";
opp-shared;
cl2_ch1_opp1: opp-115200000 {
opp-hz = /bits/ 64 <115200000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp2: opp-268800000 {
opp-hz = /bits/ 64 <268800000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp3: opp-422400000 {
opp-hz = /bits/ 64 <422400000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp4: opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp5: opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp6: opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp7: opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp8: opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp9: opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <1632000>;
};
cl2_ch1_opp10: opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <1632000>;
};
cl2_ch1_opp11: opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-peak-kBps = <2660000>;
};
cl2_ch1_opp12: opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <2660000>;
};
cl2_ch1_opp13: opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <3200000>;
};
cl2_ch1_opp14: opp-2112000000 {
opp-hz = /bits/ 64 <2112000000>;
opp-peak-kBps = <6400000>;
};
cl2_ch1_opp15: opp-2201600000 {
opp-hz = /bits/ 64 <2201600000>;
opp-peak-kBps = <6400000>;
};
};
};
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