Commit 15e3ae36 authored by 周琰杰 (Zhou Yanjie)'s avatar 周琰杰 (Zhou Yanjie) Committed by Stephen Boyd

clk: Ingenic: Remove unnecessary spinlock when reading registers.

It is not necessary to use spinlock when reading registers,
so remove it from cgu.c.
Suggested-by: default avatarPaul Cercueil <paul@crapouillou.net>
Suggested-by: default avatarPaul Burton <paulburton@kernel.org>
Signed-off-by: default avatar周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: default avatarPaul Cercueil <paul@crapouillou.net>
Link: https://lkml.kernel.org/r/20200528031549.13846-2-zhouyanjie@wanyeetech.comSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 8f3d9f35
...@@ -76,16 +76,13 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ...@@ -76,16 +76,13 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
const struct ingenic_cgu_pll_info *pll_info; const struct ingenic_cgu_pll_info *pll_info;
unsigned m, n, od_enc, od; unsigned m, n, od_enc, od;
bool bypass; bool bypass;
unsigned long flags;
u32 ctl; u32 ctl;
clk_info = &cgu->clock_info[ingenic_clk->idx]; clk_info = &cgu->clock_info[ingenic_clk->idx];
BUG_ON(clk_info->type != CGU_CLK_PLL); BUG_ON(clk_info->type != CGU_CLK_PLL);
pll_info = &clk_info->pll; pll_info = &clk_info->pll;
spin_lock_irqsave(&cgu->lock, flags);
ctl = readl(cgu->base + pll_info->reg); ctl = readl(cgu->base + pll_info->reg);
spin_unlock_irqrestore(&cgu->lock, flags);
m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0);
m += pll_info->m_offset; m += pll_info->m_offset;
...@@ -259,12 +256,9 @@ static int ingenic_pll_is_enabled(struct clk_hw *hw) ...@@ -259,12 +256,9 @@ static int ingenic_pll_is_enabled(struct clk_hw *hw)
struct ingenic_cgu *cgu = ingenic_clk->cgu; struct ingenic_cgu *cgu = ingenic_clk->cgu;
const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
unsigned long flags;
u32 ctl; u32 ctl;
spin_lock_irqsave(&cgu->lock, flags);
ctl = readl(cgu->base + pll_info->reg); ctl = readl(cgu->base + pll_info->reg);
spin_unlock_irqrestore(&cgu->lock, flags);
return !!(ctl & BIT(pll_info->enable_bit)); return !!(ctl & BIT(pll_info->enable_bit));
} }
...@@ -562,16 +556,12 @@ static int ingenic_clk_is_enabled(struct clk_hw *hw) ...@@ -562,16 +556,12 @@ static int ingenic_clk_is_enabled(struct clk_hw *hw)
struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
struct ingenic_cgu *cgu = ingenic_clk->cgu; struct ingenic_cgu *cgu = ingenic_clk->cgu;
const struct ingenic_cgu_clk_info *clk_info; const struct ingenic_cgu_clk_info *clk_info;
unsigned long flags;
int enabled = 1; int enabled = 1;
clk_info = &cgu->clock_info[ingenic_clk->idx]; clk_info = &cgu->clock_info[ingenic_clk->idx];
if (clk_info->type & CGU_CLK_GATE) { if (clk_info->type & CGU_CLK_GATE)
spin_lock_irqsave(&cgu->lock, flags);
enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate); enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate);
spin_unlock_irqrestore(&cgu->lock, flags);
}
return enabled; return enabled;
} }
......
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