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Commit 162b5250 authored by David S. Miller's avatar David S. Miller
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Merge nuts.ninka.net:/home/davem/src/BK/network-2.5 

into nuts.ninka.net:/home/davem/src/BK/net-2.5
parents 4826833f 2ec18910
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CREDITS
View file @ 162b5250
......@@ -3492,9 +3492,9 @@ S: Italy
N: Marc Zyngier
E: maz@wild-wind.fr.eu.org
W: http://www.misterjones.org
D: MD driver
S: 11 rue Victor HUGO
S: 95560 Montsoult
D: EISA/sysfs subsystem
S: France
# Don't add your name here, unless you really _are_ after Marc
......
Documentation/cpu-freq/cpu-drivers.txt
View file @ 162b5250
......@@ -35,7 +35,7 @@ Contents:
So, you just got a brand-new CPU / chipset with datasheets and want to
add cpufreq support for this CPU / chipset? Great. Here are some hints
on what is neccessary:
on what is necessary:
1.1 Initialization
......@@ -54,7 +54,7 @@ cpufreq_driver.name - The name of this driver.
cpufreq_driver.init - A pointer to the per-CPU initialization
function.
cpufreq_driver.verify - A pointer to a "verfication" funciton.
cpufreq_driver.verify - A pointer to a "verification" funciton.
cpufreq_driver.setpolicy _or_
cpufreq_driver.target - See below on the differences.
......@@ -72,7 +72,7 @@ cpufreq_driver.attr - A pointer to a NULL-terminated list of
--------------------------
Whenever a new CPU is registered with the device model, or after the
cpufreq driver registers itself, the per-CPU initialization fucntion
cpufreq driver registers itself, the per-CPU initialization function
cpufreq_driver.init is called. It takes a struct cpufreq_policy
*policy as argument. What to do now?
......@@ -94,7 +94,7 @@ policy->cur The current operating frequency of
this CPU (if appropriate)
policy->min,
policy->max,
policy->policy and, if neccessary,
policy->policy and, if necessary,
policy->governor must contain the "default policy" for
this CPU. A few moments later,
cpufreq_driver.verify and either
......
Documentation/cpu-freq/governors.txt
View file @ 162b5250
......@@ -98,7 +98,7 @@ scaling_max_freq.
-------------
The CPUfreq governor "userspace" allows the user, or any userspace
program running with UID "root", to set the CPU to a specifc frequency
program running with UID "root", to set the CPU to a specific frequency
by making a sysfs file "scaling_setspeed" available in the CPU-device
directory.
......
Documentation/cpu-freq/user-guide.txt
View file @ 162b5250
......@@ -58,7 +58,8 @@ Intel mobile PIII [*] and Intel mobile PIII-M on certain chipsets
Intel Pentium 4, Intel Xeon
National Semiconductors Geode GX
Transmeta Crusoe
varios processors on some ACPI 2.0-compatible systems [**]
VIA Cyrix 3 / C3
various processors on some ACPI 2.0-compatible systems [**]
[*] only certain Intel mobile PIII processors are supported. If you
know that you own a speedstep-capable processor, pass the option
......@@ -81,9 +82,9 @@ UltraSPARC-III
2. "Policy" / "Governor" ?
==========================
Some CPU frequency scaling-capable processor switch between varios
Some CPU frequency scaling-capable processor switch between various
frequencies and operating voltages "on the fly" without any kernel or
user involvement. This guarantuees very fast switching to a frequency
user involvement. This guarantees very fast switching to a frequency
which is high enough to serve the user's needs, but low enough to save
power.
......@@ -93,7 +94,7 @@ power.
On these systems, all you can do is select the lower and upper
frequency limit as well as whether you want more aggressive
power-saving or more instantly avaialble processing power.
power-saving or more instantly available processing power.
2.2 Governor
......
Documentation/eisa.txt 0 → 100644
View file @ 162b5250
EISA bus support (Marc Zyngier <maz@wild-wind.fr.eu.org>)
This document groups random notes about porting EISA drivers to the
new EISA/sysfs API.
Starting from version 2.5.59, the EISA bus is almost given the same
status as other much more mainstream busses such as PCI or USB. This
has been possible through sysfs, which defines a nice enough set of
abstractions to manage busses, devices and drivers.
Although the new API is quite simple to use, converting existing
drivers to the new infrastructure is not an easy task (mostly because
detection code is generally also used to probe ISA cards). Moreover,
most EISA drivers are among the oldest Linux drivers so, as you can
imagine, some dust has settled here over the years.
The EISA infrastructure is made up of three parts :
- The bus code implements most of the generic code. It is shared
among all the architectures that the EISA code runs on. It
implements bus probing (detecting EISA cards avaible on the bus),
allocates I/O resources, allows fancy naming through sysfs, and
offers interfaces for driver to register.
- The bus root driver implements the glue between the bus hardware
and the generic bus code. It is responsible for discovering the
device implementing the bus, and setting it up to be latter probed
by the bus code. This can go from something as simple as reserving
an I/O region on x86, to the rather more complex, like the hppa
EISA code. This is the part to implement in order to have EISA
running on an "new" platform.
- The driver offers the bus a list of devices that it manages, and
implements the necessary callbacks to probe and release devices
whenever told to.
Every function/structure below lives in <linux/eisa.h>, which depends
heavily on <linux/device.h>.
** Bus root driver :
int eisa_root_register (struct eisa_root_device *root);
The eisa_root_register function is used to declare a device as the
root of an EISA bus. The eisa_root_device structure holds a reference
to this device, as well as some parameters for probing purposes.
struct eisa_root_device {
struct list_head node;
struct device *dev; /* Pointer to bridge device */
struct resource *res;
unsigned long bus_base_addr;
int slots; /* Max slot number */
int bus_nr; /* Set by eisa_root_register */
};
node : used for eisa_root_register internal purpose
dev : pointer to the root device
res : root device I/O resource
bus_base_addr : slot 0 address on this bus
slots : max slot number to probe
bus_nr : unique bus id, set by eisa_root_register
** Driver :
int eisa_driver_register (struct eisa_driver *edrv);
void eisa_driver_unregister (struct eisa_driver *edrv);
Clear enough ?
struct eisa_device_id {
char sig[EISA_SIG_LEN];
unsigned long driver_data;
};
struct eisa_driver {
const struct eisa_device_id *id_table;
struct device_driver driver;
};
id_table : an array of NULL terminated EISA id strings,
followed by an empty string. Each string can be
paired with a driver-dependant value (driver_data).
driver : a generic driver, such as described in
Documentation/driver-model/driver.txt. Only .name,
.probe and .remove members are mandatory.
An example is the 3c509 driver :
struct eisa_device_id el3_eisa_ids[] = {
{ "TCM5092" },
{ "TCM5093" },
{ "" }
};
struct eisa_driver el3_eisa_driver = {
.id_table = el3_eisa_ids,
.driver = {
.name = "3c509",
.probe = el3_eisa_probe,
.remove = __devexit_p (el3_device_remove)
}
};
** Device :
The sysfs framework calls .probe and .remove functions upon device
discovery and removal (note that the .remove function is only called
when driver is built as a module).
Both functions are passed a pointer to a 'struct device', which is
encapsulated in a 'struct eisa_device' described as follows :
struct eisa_device {
struct eisa_device_id id;
int slot;
unsigned long base_addr;
struct resource res;
struct device dev; /* generic device */
};
id : EISA id, as read from device. id.driver_data is set from the
matching driver EISA id.
slot : slot number which the device was detected on
res : I/O resource allocated to this device
dev : generic device (see Documentation/driver-model/device.txt)
You can get the 'struct eisa_device' from 'struct device' using the
'to_eisa_device' macro.
** Misc stuff :
void eisa_set_drvdata (struct eisa_device *edev, void *data);
Stores data into the device's driver_data area.
void *eisa_get_drvdata (struct eisa_device *edev):
Gets the pointer previously stored into the device's driver_data area.
** Random notes :
Converting an EISA driver to the new API mostly involves *deleting*
code (since probing is now in the core EISA code). Unfortunately, most
drivers share their probing routine between ISA, MCA and EISA. Special
care must be taken when ripping out the EISA code, so other busses
won't suffer from these surgical strikes...
You *must not* expect any EISA device to be detected when returning
from eisa_driver_register, since the chances are that the bus has not
yet been probed. In fact, that's what happens most of the time (the
bus root driver usually kicks in rather late in the boot process).
Unfortunately, most drivers are doing the probing by themselves, and
expect to have explored the whole machine when they exit their probe
routine.
** Thanks :
I'd like to thank the following people for their help :
- Xavier Benigni for lending me a wonderful Alpha Jensen,
- James Bottomley, Jeff Garzik for getting this stuff into the kernel,
- Andries Brouwer for contributing numerous EISA ids,
- Catrin Jones for coping with too many machines at home
Documentation/filesystems/devfs/README
View file @ 162b5250
......@@ -1466,13 +1466,6 @@ The simplest option (especially when porting drivers to devfs) is to
keep using the old major and minor numbers. Devfs will take whatever
values are given for major&minor and pass them onto userspace.
Alternatively, you can have devfs choose unique device numbers for
you. When you register a character or block device using
devfs_register you can provide the optional
DEVFS_FL_AUTO_DEVNUM flag, which will then automatically allocate a
unique device number (the allocation is separated for the character
and block devices).
This device number is a 16 bit number, so this leaves plenty of space
for large numbers of discs and partitions. This scheme can also be
used for character devices, in particular the tty devices, which are
......
arch/i386/boot/Makefile
View file @ 162b5250
......@@ -65,33 +65,33 @@ $(obj)/compressed/vmlinux: FORCE
# Set this if you want to pass append arguments to the zdisk/fdimage kernel
FDARGS =
$(obj)/mtools.conf: $(obj)/mtools.conf.in
$(obj)/mtools.conf: $(src)/mtools.conf.in
sed -e 's|@OBJ@|$(obj)|g' < $< > $@
# This requires write access to /dev/fd0
zdisk: $(BOOTIMAGE) $(obj)/mtools.conf
MTOOLSRC=$(src)/mtools.conf mformat a: ; sync
MTOOLSRC=$(obj)/mtools.conf mformat a: ; sync
syslinux /dev/fd0 ; sync
echo 'default linux $(FDARGS)' | \
MTOOLSRC=$(src)/mtools.conf mcopy - a:syslinux.cfg
MTOOLSRC=$(src)/mtools.conf mcopy $(BOOTIMAGE) a:linux ; sync
MTOOLSRC=$(obj)/mtools.conf mcopy $(BOOTIMAGE) a:linux ; sync
# These require being root or having syslinux 2.02 or higher installed
fdimage fdimage144: $(BOOTIMAGE) $(src)/mtools.conf
fdimage fdimage144: $(BOOTIMAGE) $(obj)/mtools.conf
dd if=/dev/zero of=$(obj)/fdimage bs=1024 count=1440
MTOOLSRC=$(src)/mtools.conf mformat v: ; sync
MTOOLSRC=$(obj)/mtools.conf mformat v: ; sync
syslinux $(obj)/fdimage ; sync
echo 'default linux $(FDARGS)' | \
MTOOLSRC=$(src)/mtools.conf mcopy - v:syslinux.cfg
MTOOLSRC=$(src)/mtools.conf mcopy $(BOOTIMAGE) v:linux ; sync
MTOOLSRC=$(obj)/mtools.conf mcopy - v:syslinux.cfg
MTOOLSRC=$(obj)/mtools.conf mcopy $(BOOTIMAGE) v:linux ; sync
fdimage288: $(BOOTIMAGE) $(src)/mtools.conf
fdimage288: $(BOOTIMAGE) $(obj)/mtools.conf
dd if=/dev/zero of=$(obj)/fdimage bs=1024 count=2880
MTOOLSRC=$(src)/mtools.conf mformat w: ; sync
MTOOLSRC=$(obj)/mtools.conf mformat w: ; sync
syslinux $(obj)/fdimage ; sync
echo 'default linux $(FDARGS)' | \
MTOOLSRC=$(src)/mtools.conf mcopy - w:syslinux.cfg
MTOOLSRC=$(src)/mtools.conf mcopy $(BOOTIMAGE) w:linux ; sync
MTOOLSRC=$(obj)/mtools.conf mcopy - w:syslinux.cfg
MTOOLSRC=$(obj)/mtools.conf mcopy $(BOOTIMAGE) w:linux ; sync
zlilo: $(BOOTIMAGE)
if [ -f $(INSTALL_PATH)/vmlinuz ]; then mv $(INSTALL_PATH)/vmlinuz $(INSTALL_PATH)/vmlinuz.old; fi
......
arch/i386/kernel/cpu/cpufreq/powernow-k7.c
View file @ 162b5250
......@@ -239,12 +239,17 @@ static void change_speed (unsigned int index)
__asm__("\tcli\n");
rdmsrl (MSR_K7_FID_VID_CTL, fidvidctl.val);
fidvidctl.bits.SGTC = latency; /* Stop grant timeout counter */
fidvidctl.bits.FID = fid;
fidvidctl.bits.VID = vid;
/* Note, we could set these lazily. Ie, only do voltage transition
if its changed since last time (Some speeds have the same voltage) */
fidvidctl.bits.FIDC = 1;
fidvidctl.bits.VIDC = 1;
/* Set the voltage lazily. Ie, only do voltage transition
if its changed since last time (Some speeds have the same voltage) */
if (fidvidctl.bits.VID != vid) {
fidvidctl.bits.VID = vid;
fidvidctl.bits.VIDC = 1;
}
wrmsrl (MSR_K7_FID_VID_CTL, fidvidctl.val);
if (have_a0 == 1)
__asm__("\tsti\n");
......
arch/i386/kernel/entry.S
View file @ 162b5250
......@@ -72,6 +72,12 @@ DF_MASK = 0x00000400
NT_MASK = 0x00004000
VM_MASK = 0x00020000
/*
* ESP0 is at offset 4. 0x100 is the size of the TSS, and
* also thus the top-of-stack pointer offset of SYSENTER_ESP
*/
TSS_ESP0_OFFSET = (4 - 0x100)
#ifdef CONFIG_PREEMPT
#define preempt_stop cli
#else
......@@ -229,6 +235,8 @@ need_resched:
# sysenter call handler stub
ENTRY(sysenter_entry)
movl TSS_ESP0_OFFSET(%esp),%esp
sysenter_past_esp:
sti
pushl $(__USER_DS)
pushl %ebp
......@@ -458,12 +466,36 @@ device_not_available_emulate:
addl $4, %esp
jmp ret_from_exception
/*
* Debug traps and NMI can happen at the one SYSENTER instruction
* that sets up the real kernel stack. Check here, since we can't
* allow the wrong stack to be used.
*
* "TSS_ESP0_OFFSET+12" is because the NMI/debug handler will have
* already pushed 3 words if it hits on the sysenter instruction:
* eflags, cs and eip.
*
* We just load the right stack, and push the three (known) values
* by hand onto the new stack - while updating the return eip past
* the instruction that would have done it for sysenter.
*/
#define CHECK_SYSENTER_EIP \
cmpl $sysenter_entry,(%esp); \
jne 1f; \
movl TSS_ESP0_OFFSET+12(%esp),%esp; \
pushfl; \
pushl $__KERNEL_CS; \
pushl $sysenter_past_esp; \
1:
ENTRY(debug)
CHECK_SYSENTER_EIP
pushl $0
pushl $do_debug
jmp error_code
ENTRY(nmi)
CHECK_SYSENTER_EIP
pushl %eax
SAVE_ALL
movl %esp, %edx
......
arch/i386/kernel/microcode.c
View file @ 162b5250
......@@ -372,7 +372,6 @@ static ssize_t microcode_write(struct file *file, const char *buf, size_t len, l
ret = (ssize_t)len;
}
out_fsize:
devfs_set_file_size(devfs_handle, mc_fsize);
vfree(microcode);
out_unlock:
up_write(&microcode_rwsem);
......@@ -388,7 +387,6 @@ static int microcode_ioctl(struct inode *inode, struct file *file,
if (mc_applied) {
int bytes = NR_CPUS * sizeof(struct microcode);
devfs_set_file_size(devfs_handle, 0);
kfree(mc_applied);
mc_applied = NULL;
printk(KERN_INFO "microcode: freed %d bytes\n", bytes);
......
arch/i386/kernel/sysenter.c
View file @ 162b5250
......@@ -41,8 +41,9 @@ void enable_sep_cpu(void *info)
struct tss_struct *tss = init_tss + cpu;
tss->ss1 = __KERNEL_CS;
tss->esp1 = sizeof(struct tss_struct) + (unsigned long) tss;
wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0);
wrmsr(MSR_IA32_SYSENTER_ESP, tss->esp0, 0);
wrmsr(MSR_IA32_SYSENTER_ESP, tss->esp1, 0);
wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long) sysenter_entry, 0);
printk("Enabling SEP on CPU %d\n", cpu);
......
arch/m68knommu/Kconfig
View file @ 162b5250
......@@ -102,7 +102,7 @@ config CLOCK_AUTO
really need to know, so you can select the AUTO option. On some
boards you need to know the real clock frequency to determine other
system timing (for example baud rate dividors, etc). Some processors
have an internal PLL and you can seletc a frequency to set that too.
have an internal PLL and you can select a frequency to run at.
You need to know a little about the internals of your processor to
set this. If in doubt choose the AUTO option.
......@@ -675,11 +675,12 @@ config FULLDEBUG
config MAGIC_SYSRQ
bool "Magic SysRq key"
help
Enables console device to interprent special characters as
Enables console device to interpret special characters as
commands to dump state information.
config HIGHPROFILE
bool "Use fast second timer for profiling"
depends on COLDFIRE
help
Use a fast secondary clock to produce profiling information.
......@@ -699,7 +700,7 @@ config BDM_DISABLE
bool "Disable BDM signals"
depends on (EXPERIMENTAL && COLDFIRE)
help
Disable the CPU's BDM signals.
Disable the ColdFire CPU's BDM signals.
endmenu
......
arch/m68knommu/kernel/comempci.c
View file @ 162b5250
......@@ -3,7 +3,7 @@
/*
* comemlite.c -- PCI access code for embedded CO-MEM Lite PCI controller.
*
* (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com).
* (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com).
* (C) Copyright 2000, Lineo (www.lineo.com)
*/
......@@ -60,8 +60,8 @@ unsigned long pci_slotmask = 0;
* really assign any resources we like to devices, as long as
* they do not clash with other PCI devices.
*/
unsigned int pci_iobase = 0x100; /* Arbitary start address */
unsigned int pci_membase = 0x00010000; /* Arbitary start address */
unsigned int pci_iobase = PCIBIOS_MIN_IO; /* Arbitary start address */
unsigned int pci_membase = PCIBIOS_MIN_MEM; /* Arbitary start address */
#define PCI_MINIO 0x100 /* 256 byte minimum I/O */
#define PCI_MINMEM 0x00010000 /* 64k minimum chunk */
......@@ -75,7 +75,7 @@ unsigned int pci_shmemaddr;
/*****************************************************************************/
void pci_interrupt(int irq, void *id, struct pt_regs *fp);
void pci_interrupt(int irq, void *id, struct pt_regs *fp);
/*****************************************************************************/
......@@ -105,7 +105,7 @@ void pci_resetbus(void)
/*****************************************************************************/
int pcibios_assignres(int slot)
int pcibios_assign_resource_slot(int slot)
{
volatile unsigned long *rp;
volatile unsigned char *ip;
......@@ -113,7 +113,7 @@ int pcibios_assignres(int slot)
int bar;
#ifdef DEBUGPCI
printk("pcibios_assignres(slot=%x)\n", slot);
printk("pcibios_assign_resource_slot(slot=%x)\n", slot);
#endif
rp = (volatile unsigned long *) COMEM_BASE;
......@@ -224,7 +224,7 @@ int pcibios_assignres(int slot)
/*****************************************************************************/
int pcibios_enable(int slot)
int pcibios_enable_slot(int slot)
{
volatile unsigned long *rp;
volatile unsigned short *wp;
......@@ -232,7 +232,7 @@ int pcibios_enable(int slot)
unsigned short cmd;
#ifdef DEBUGPCI
printk("pcibios_enbale(slot=%x)\n", slot);
printk("pcibios_enbale_slot(slot=%x)\n", slot);
#endif
rp = (volatile unsigned long *) COMEM_BASE;
......@@ -256,7 +256,34 @@ int pcibios_enable(int slot)
/*****************************************************************************/
unsigned long pcibios_init(unsigned long mem_start, unsigned long mem_end)
void pcibios_assign_resources(void)
{
volatile unsigned long *rp;
unsigned long sel, id;
int slot;
rp = (volatile unsigned long *) COMEM_BASE;
/*
* Do a quick scan of the PCI bus and see what is here.
*/
for (slot = COMEM_MINDEV; (slot <= COMEM_MAXDEV); slot++) {
sel = COMEM_DA_CFGRD | COMEM_DA_ADDR(0x1 << (slot + 16));
rp[LREG(COMEM_DAHBASE)] = sel;
rp[LREG(COMEM_PCIBUS)] = 0; /* Clear bus */
id = rp[LREG(COMEM_PCIBUS)];
if ((id != 0) && ((id & 0xffff0000) != (sel & 0xffff0000))) {
printk("PCI: slot=%d id=%08x\n", slot, (int) id);
pci_slotmask |= 0x1 << slot;
pcibios_assign_resource_slot(slot);
pcibios_enable_slot(slot);
}
}
}
/*****************************************************************************/
int pcibios_init(void)
{
volatile unsigned long *rp;
unsigned long sel, id;
......@@ -276,7 +303,7 @@ unsigned long pcibios_init(unsigned long mem_start, unsigned long mem_end)
rp = (volatile unsigned long *) COMEM_BASE;
if ((rp[LREG(COMEM_LBUSCFG)] & 0xff) != 0x50) {
printk("PCI: no PCI bus present\n");
return(mem_start);
return(0);
}
#ifdef COMEM_BRIDGEDEV
......@@ -291,34 +318,18 @@ unsigned long pcibios_init(unsigned long mem_start, unsigned long mem_end)
id = rp[LREG(COMEM_PCIBUS)];
if ((id == 0) || ((id & 0xffff0000) == (sel & 0xffff0000))) {
printk("PCI: no PCI bus bridge present\n");
return(mem_start);
return(0);
}
printk("PCI: bridge device at slot=%d id=%08x\n", slot, (int) id);
pci_slotmask |= 0x1 << slot;
pci_shmemaddr = pci_membase;
pcibios_assignres(slot);
pcibios_enable(slot);
pcibios_assign_resource_slot(slot);
pcibios_enable_slot(slot);
#endif
pci_bus_is_present = 1;
/*
* Do a quick scan of the PCI bus and see what is here.
*/
for (slot = COMEM_MINDEV; (slot <= COMEM_MAXDEV); slot++) {
sel = COMEM_DA_CFGRD | COMEM_DA_ADDR(0x1 << (slot + 16));
rp[LREG(COMEM_DAHBASE)] = sel;
rp[LREG(COMEM_PCIBUS)] = 0; /* Clear bus */
id = rp[LREG(COMEM_PCIBUS)];
if ((id != 0) && ((id & 0xffff0000) != (sel & 0xffff0000))) {
printk("PCI: slot=%d id=%08x\n", slot, (int) id);
pci_slotmask |= 0x1 << slot;
pcibios_assignres(slot);
pcibios_enable(slot);
}
}
/* Get PCI irq for local vectoring */
if (request_irq(COMEM_IRQ, pci_interrupt, 0, "PCI bridge", NULL)) {
printk("PCI: failed to acquire interrupt %d\n", COMEM_IRQ);
......@@ -326,16 +337,53 @@ unsigned long pcibios_init(unsigned long mem_start, unsigned long mem_end)
mcf_autovector(COMEM_IRQ);
}
return(mem_start);
pcibios_assign_resources();
return(0);
}
/*****************************************************************************/
unsigned long pcibios_fixup(unsigned long mem_start, unsigned long mem_end)
char *pcibios_setup(char *option)
{
/* Nothing for us to handle. */
return(option);
}
/*****************************************************************************/
struct pci_fixup pcibios_fixups[] = { { 0 } };
void pcibios_fixup_bus(struct pci_bus *b)
{
return(mem_start);
}
/*****************************************************************************/
void pcibios_align_resource(void *data, struct resource *res, unsigned long size, unsigned long align)
{
}
/*****************************************************************************/
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
int slot;
slot = PCI_SLOT(dev->devfn);
if ((dev->bus == 0) && (pci_slotmask & (1 << slot)))
pcibios_enable_slot(slot);
return(0);
}
/*****************************************************************************/
void pcibios_update_resource(struct pci_dev *dev, struct resource *root, struct resource *r, int resource)
{
printk("%s(%d): no support for changing PCI resources...\n",
__FILE__, __LINE__);
}
/*****************************************************************************/
/*
......@@ -921,3 +969,23 @@ void pci_bmcpyfrom(void *dst, void *src, int len)
}
/*****************************************************************************/
void *pci_alloc_consistent(struct pci_dev *dev, size_t size, dma_addr_t *dma_addr)
{
void *mp;
if ((mp = pci_bmalloc(size)) != NULL) {
dma_addr = mp - (COMEM_BASE + COMEM_SHMEM);
return(mp);
}
*dma_addr = (dma_addr_t) NULL;
return(NULL);
}
/*****************************************************************************/
void pci_free_consistent(struct pci_dev *dev, size_t size, void *cpu_addr, dma_addr_t dma_addr)
{
pci_bmfree(cpu_addr, size);
}
/*****************************************************************************/
arch/m68knommu/kernel/entry.S
View file @ 162b5250
......@@ -84,6 +84,9 @@ ENTRY(reschedule)
jmp schedule
ENTRY(ret_from_fork)
movel %d1,%sp@-
jsr schedule_tail
addql #4,%sp
jra ret_from_exception
ENTRY(sys_fork)
......
arch/m68knommu/platform/5206/config.c
View file @ 162b5250
......@@ -25,6 +25,14 @@
/***************************************************************************/
void coldfire_tick(void);
void coldfire_timer_init(void (*handler)(int, void *, struct pt_regs *));
unsigned long coldfire_timer_offset(void);
void coldfire_trap_init(void);
void coldfire_reset(void);
/***************************************************************************/
/*
* DMA channel base address table.
*/
......@@ -33,47 +41,8 @@ unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = {
MCF_MBAR + MCFDMA_BASE1,
};
unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
/***************************************************************************/
void coldfire_tick(void)
{
volatile unsigned char *timerp;
/* Reset the ColdFire timer */
timerp = (volatile unsigned char *) (MCF_MBAR + MCFTIMER_BASE1);
timerp[MCFTIMER_TER] = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
}
/***************************************************************************/
void coldfire_timer_init(void (*handler)(int, void *, struct pt_regs *))
{
volatile unsigned short *timerp;
volatile unsigned char *icrp;
/* Set up TIMER 1 as poll clock */
timerp = (volatile unsigned short *) (MCF_MBAR + MCFTIMER_BASE1);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_DISABLE;
timerp[MCFTIMER_TRR] = (unsigned short) ((MCF_CLK / 16) / HZ);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_TIMER1ICR);
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI3;
request_irq(29, handler, SA_INTERRUPT, "ColdFire Timer", NULL);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_TIMER1);
}
/***************************************************************************/
/*
* Program the vector to be an auto-vectored.
*/
void mcf_autovector(unsigned int vec)
{
volatile unsigned char *mbar;
......@@ -91,65 +60,35 @@ void mcf_autovector(unsigned int vec)
/***************************************************************************/
extern e_vector *_ramvec;
void set_evector(int vecnum, void (*handler)(void))
void mcf_settimericr(unsigned int timer, unsigned int level)
{
if (vecnum >= 0 && vecnum <= 255)
_ramvec[vecnum] = handler;
}
/***************************************************************************/
/* assembler routines */
asmlinkage void buserr(void);
asmlinkage void trap(void);
asmlinkage void system_call(void);
asmlinkage void inthandler(void);
void coldfire_trap_init(void)
{
int i;
#ifndef ENABLE_dBUG
mcf_setimr(MCFSIM_IMR_MASKALL);
#endif
/*
* There is a common trap handler and common interrupt
* handler that handle almost every vector. We treat
* the system call and bus error special, they get their
* own first level handlers.
*/
#ifndef ENABLE_dBUG
for (i = 3; (i <= 23); i++)
_ramvec[i] = trap;
for (i = 33; (i <= 63); i++)
_ramvec[i] = trap;
#endif
for (i = 24; (i <= 30); i++)
_ramvec[i] = inthandler;
#ifndef ENABLE_dBUG
_ramvec[31] = inthandler; // Disables the IRQ7 button
#endif
for (i = 64; (i < 255); i++)
_ramvec[i] = inthandler;
_ramvec[255] = 0;
_ramvec[2] = buserr;
_ramvec[32] = system_call;
volatile unsigned char *icrp;
unsigned int icr, imr;
if (timer <= 2) {
switch (timer) {
case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
}
icrp = (volatile unsigned char *) (MCF_MBAR + icr);
*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
mcf_setimr(mcf_getimr() & ~imr);
}
}
/***************************************************************************/
void config_BSP(char *commandp, int size)
{
mcf_setimr(MCFSIM_IMR_MASKALL);
memset(commandp, 0, size);
mach_sched_init = coldfire_timer_init;
mach_tick = coldfire_tick;
mach_gettimeoffset = coldfire_timer_offset;
mach_trap_init = coldfire_trap_init;
mach_reset = coldfire_reset;
}
/***************************************************************************/
arch/m68knommu/platform/5206e/config.c
View file @ 162b5250
......@@ -20,17 +20,16 @@
#include <asm/mcftimer.h>
#include <asm/mcfsim.h>
#include <asm/mcfdma.h>
#ifdef CONFIG_NETtel
#include <asm/irq.h>
#include <asm/delay.h>
#endif
/***************************************************************************/
#ifdef CONFIG_NETtel
void reset_setupbutton(void);
#endif
void coldfire_tick(void);
void coldfire_timer_init(void (*handler)(int, void *, struct pt_regs *));
unsigned long coldfire_timer_offset(void);
void coldfire_trap_init(void);
void coldfire_reset(void);
/***************************************************************************/
......@@ -42,53 +41,8 @@ unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = {
MCF_MBAR + MCFDMA_BASE1,
};
unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
/***************************************************************************/
void coldfire_tick(void)
{
volatile unsigned char *timerp;
/* Reset the ColdFire timer */
timerp = (volatile unsigned char *) (MCF_MBAR + MCFTIMER_BASE1);
timerp[MCFTIMER_TER] = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
}
/***************************************************************************/
void coldfire_timer_init(void (*handler)(int, void *, struct pt_regs *))
{
volatile unsigned short *timerp;
volatile unsigned char *icrp;
/* Set up TIMER 1 as poll clock */
timerp = (volatile unsigned short *) (MCF_MBAR + MCFTIMER_BASE1);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_DISABLE;
timerp[MCFTIMER_TRR] = (unsigned short) ((MCF_CLK / 16) / HZ);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_TIMER1ICR);
#ifdef CONFIG_NETtel
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3;
request_irq(30, handler, SA_INTERRUPT, "ColdFire Timer", NULL);
reset_setupbutton();
#else
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI3;
request_irq(29, handler, SA_INTERRUPT, "ColdFire Timer", NULL);
#endif
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_TIMER1);
}
/***************************************************************************/
/*
* Program the vector to be an auto-vectored.
*/
void mcf_autovector(unsigned int vec)
{
volatile unsigned char *mbar;
......@@ -106,117 +60,29 @@ void mcf_autovector(unsigned int vec)
/***************************************************************************/
extern e_vector *_ramvec;
void set_evector(int vecnum, void (*handler)(void))
void mcf_settimericr(unsigned int timer, unsigned int level)
{
if (vecnum >= 0 && vecnum <= 255)
_ramvec[vecnum] = handler;
}
/***************************************************************************/
/* assembler routines */
asmlinkage void buserr(void);
asmlinkage void trap(void);
asmlinkage void system_call(void);
asmlinkage void inthandler(void);
void coldfire_trap_init(void)
{
int i;
#ifdef MCF_MEMORY_PROTECT
extern unsigned long _end;
extern unsigned long memory_end;
#endif
#ifndef ENABLE_dBUG
mcf_setimr(MCFSIM_IMR_MASKALL);
#endif
/*
* There is a common trap handler and common interrupt
* handler that handle almost every vector. We treat
* the system call and bus error special, they get their
* own first level handlers.
*/
#ifndef ENABLE_dBUG
for (i = 3; (i <= 23); i++)
_ramvec[i] = trap;
for (i = 33; (i <= 63); i++)
_ramvec[i] = trap;
#endif
for (i = 24; (i <= 30); i++)
_ramvec[i] = inthandler;
#ifndef ENABLE_dBUG
_ramvec[31] = inthandler; // Disables the IRQ7 button
#endif
for (i = 64; (i < 255); i++)
_ramvec[i] = inthandler;
_ramvec[255] = 0;
_ramvec[2] = buserr;
_ramvec[32] = system_call;
}
/***************************************************************************/
#ifdef CONFIG_NETtel
/*
* Routines to support the NETtel software reset button.
*/
void reset_button(int irq, void *dev_id, struct pt_regs *regs)
{
extern void flash_eraseconfig(void);
static int inbutton = 0;
/*
* IRQ7 is not maskable by the CPU core. It is possible
* that switch bounce may get us back here before we have
* really serviced the interrupt.
*/
if (inbutton)
return;
inbutton = 1;
/* Disable interrupt at SIM - best we can do... */
mcf_setimr(mcf_getimr() | MCFSIM_IMR_EINT7);
/* Try and de-bounce the switch a little... */
udelay(10000);
flash_eraseconfig();
/* Don't leave here 'till button is no longer pushed! */
for (;;) {
if ((mcf_getipr() & MCFSIM_IMR_EINT7) == 0)
break;
volatile unsigned char *icrp;
unsigned int icr, imr;
if (timer <= 2) {
switch (timer) {
case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
}
icrp = (volatile unsigned char *) (MCF_MBAR + icr);
*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
mcf_setimr(mcf_getimr() & ~imr);
}
HARD_RESET_NOW();
/* Should never get here... */
inbutton = 0;
/* Interrupt service done, enable it again */
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT7);
}
/***************************************************************************/
void reset_setupbutton(void)
{
mcf_autovector(31);
request_irq(31, reset_button, (SA_INTERRUPT | IRQ_FLG_FAST),
"Reset Button", NULL);
}
#endif /* CONFIG_NETtel */
/***************************************************************************/
void config_BSP(char *commandp, int size)
{
mcf_setimr(MCFSIM_IMR_MASKALL);
#ifdef CONFIG_NETtel
/* Copy command line from FLASH to local buffer... */
memcpy(commandp, (char *) 0xf0004000, size);
......@@ -227,7 +93,9 @@ void config_BSP(char *commandp, int size)
mach_sched_init = coldfire_timer_init;
mach_tick = coldfire_tick;
mach_gettimeoffset = coldfire_timer_offset;
mach_trap_init = coldfire_trap_init;
mach_reset = coldfire_reset;
}
/***************************************************************************/
arch/m68knommu/platform/5249/config.c
View file @ 162b5250
......@@ -25,7 +25,11 @@
/***************************************************************************/
void coldfire_profile_init(void);
void coldfire_tick(void);
void coldfire_timer_init(void (*handler)(int, void *, struct pt_regs *));
unsigned long coldfire_timer_offset(void);
void coldfire_trap_init(void);
void coldfire_reset(void);
/***************************************************************************/
......@@ -39,104 +43,7 @@ unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = {
MCF_MBAR + MCFDMA_BASE3,
};
unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
/***************************************************************************/
void coldfire_tick(void)
{
volatile unsigned char *timerp;
/* Reset the ColdFire timer */
timerp = (volatile unsigned char *) (MCF_MBAR + MCFTIMER_BASE1);
timerp[MCFTIMER_TER] = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
}
/***************************************************************************/
void coldfire_timer_init(void (*handler)(int, void *, struct pt_regs *))
{
volatile unsigned short *timerp;
volatile unsigned char *icrp;
/* Set up TIMER 1 as poll clock */
timerp = (volatile unsigned short *) (MCF_MBAR + MCFTIMER_BASE1);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_DISABLE;
timerp[MCFTIMER_TRR] = (unsigned short) ((MCF_CLK / 16) / HZ);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_TIMER1ICR);
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI3;
request_irq(29, handler, SA_INTERRUPT, "ColdFire Timer", NULL);
#ifdef CONFIG_HIGHPROFILE
coldfire_profile_init();
#endif
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_TIMER1);
}
/***************************************************************************/
#ifdef CONFIG_HIGHPROFILE
/***************************************************************************/
#define PROFILEHZ 1013
/*
* Use the other timer to provide high accuracy profiling info.
*/
void coldfire_profile_tick(int irq, void *dummy, struct pt_regs *regs)
{
volatile unsigned char *timerp;
/* Reset the ColdFire timer2 */
timerp = (volatile unsigned char *) (MCF_MBAR + MCFTIMER_BASE2);
timerp[MCFTIMER_TER] = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
if (!user_mode(regs)) {
if (prof_buffer && current->pid) {
extern int _stext;
unsigned long ip = instruction_pointer(regs);
ip -= (unsigned long) &_stext;
ip >>= prof_shift;
if (ip < prof_len)
prof_buffer[ip]++;
}
}
}
void coldfire_profile_init(void)
{
volatile unsigned short *timerp;
volatile unsigned char *icrp;
printk("PROFILE: lodging timer2=%d as profile timer\n", PROFILEHZ);
/* Set up TIMER 2 as poll clock */
timerp = (volatile unsigned short *) (MCF_MBAR + MCFTIMER_BASE2);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_DISABLE;
timerp[MCFTIMER_TRR] = (unsigned short) ((MCF_CLK / 16) / PROFILEHZ);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_TIMER2ICR);
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3;
request_irq(31, coldfire_profile_tick, (SA_INTERRUPT | IRQ_FLG_FAST),
"Profile Timer", NULL);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_TIMER2);
}
/***************************************************************************/
#endif /* CONFIG_HIGHPROFILE */
/***************************************************************************/
/*
* Program the vector to be an auto-vectored.
*/
void mcf_autovector(unsigned int vec)
{
......@@ -152,78 +59,35 @@ void mcf_autovector(unsigned int vec)
/***************************************************************************/
extern e_vector *_ramvec;
void set_evector(int vecnum, void (*handler)(void))
void mcf_settimericr(unsigned int timer, unsigned int level)
{
if (vecnum >= 0 && vecnum <= 255)
_ramvec[vecnum] = handler;
}
/***************************************************************************/
/* assembler routines */
asmlinkage void buserr(void);
asmlinkage void trap(void);
asmlinkage void system_call(void);
asmlinkage void inthandler(void);
void __init coldfire_trap_init(void)
{
int i;
#ifndef ENABLE_dBUG
mcf_setimr(MCFSIM_IMR_MASKALL);
#endif
/*
* There is a common trap handler and common interrupt
* handler that handle almost every vector. We treat
* the system call and bus error special, they get their
* own first level handlers.
*/
#ifndef ENABLE_dBUG
for (i = 3; (i <= 23); i++)
_ramvec[i] = trap;
for (i = 33; (i <= 63); i++)
_ramvec[i] = trap;
#endif
for (i = 24; (i <= 30); i++)
_ramvec[i] = inthandler;
#ifndef ENABLE_dBUG
_ramvec[31] = inthandler; // Disables the IRQ7 button
#endif
for (i = 64; (i < 255); i++)
_ramvec[i] = inthandler;
_ramvec[255] = 0;
_ramvec[2] = buserr;
_ramvec[32] = system_call;
volatile unsigned char *icrp;
unsigned int icr, imr;
if (timer <= 2) {
switch (timer) {
case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
}
icrp = (volatile unsigned char *) (MCF_MBAR + icr);
*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
mcf_setimr(mcf_getimr() & ~imr);
}
}
/***************************************************************************/
void config_BSP(char *commandp, int size)
{
mcf_setimr(MCFSIM_IMR_MASKALL);
memset(commandp, 0, size);
mach_sched_init = coldfire_timer_init;
mach_tick = coldfire_tick;
mach_gettimeoffset = coldfire_timer_offset;
mach_trap_init = coldfire_trap_init;
mach_reset = coldfire_reset;
}
/***************************************************************************/
#ifdef TRAP_DBG_INTERRUPT
asmlinkage void dbginterrupt_c(struct frame *fp)
{
extern void dump(struct pt_regs *fp);
printk("%s(%d): BUS ERROR TRAP\n", __FILE__, __LINE__);
dump((struct pt_regs *) fp);
asm("halt");
}
#endif
/***************************************************************************/
arch/m68knommu/platform/5272/config.c
View file @ 162b5250
......@@ -26,7 +26,15 @@
/***************************************************************************/
void reset_setupbutton(void);
void coldfire_tick(void);
void coldfire_timer_init(void (*handler)(int, void *, struct pt_regs *));
unsigned long coldfire_timer_offset(void);
void coldfire_trap_init(void);
void coldfire_reset(void);
extern unsigned int mcf_timervector;
extern unsigned int mcf_profilevector;
extern unsigned int mcf_timerlevel;
/***************************************************************************/
......@@ -37,50 +45,21 @@ unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = {
MCF_MBAR + MCFDMA_BASE0,
};
unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
/***************************************************************************/
void coldfire_tick(void)
void mcf_disableall(void)
{
volatile unsigned char *timerp;
/* Reset the ColdFire timer */
timerp = (volatile unsigned char *) (MCF_MBAR + MCFTIMER_BASE4);
timerp[MCFTIMER_TER] = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
}
/***************************************************************************/
void coldfire_timer_init(void (*handler)(int, void *, struct pt_regs *))
{
volatile unsigned short *timerp;
volatile unsigned long *icrp;
/* Set up TIMER 4 as poll clock */
timerp = (volatile unsigned short *) (MCF_MBAR + MCFTIMER_BASE4);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_DISABLE;
timerp[MCFTIMER_TRR] = (unsigned short) ((MCF_CLK / 16) / HZ);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
*icrp = 0x0000000d; /* TMR4 with priority 5 */
request_irq(72, handler, SA_INTERRUPT, "ColdFire Timer", NULL);
#ifdef CONFIG_RESETSWITCH
/* This is not really the right place to do this... */
reset_setupbutton();
#endif
icrp[0] = 0x88888888;
icrp[1] = 0x88888888;
icrp[2] = 0x88888888;
icrp[3] = 0x88888888;
}
/***************************************************************************/
/*
* Program the vector to be an auto-vectored.
*/
void mcf_autovector(unsigned int vec)
{
/* Everything is auto-vectored on the 5272 */
......@@ -88,68 +67,20 @@ void mcf_autovector(unsigned int vec)
/***************************************************************************/
extern e_vector *_ramvec;
void set_evector(int vecnum, void (*handler)(void))
void mcf_settimericr(int timer, int level)
{
if (vecnum >= 0 && vecnum <= 255)
_ramvec[vecnum] = handler;
}
/***************************************************************************/
/* assembler routines */
asmlinkage void buserr(void);
asmlinkage void trap(void);
asmlinkage void system_call(void);
asmlinkage void inthandler(void);
void coldfire_trap_init(void)
{
int i;
#ifndef ENABLE_dBUG
volatile unsigned long *icrp;
icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
icrp[0] = 0x88888888;
icrp[1] = 0x88888888;
icrp[2] = 0x88888888;
icrp[3] = 0x88888888;
#endif
/*
* There is a common trap handler and common interrupt
* handler that handle almost every vector. We treat
* the system call and bus error special, they get their
* own first level handlers.
*/
#ifndef ENABLE_dBUG
for (i = 3; (i <= 23); i++)
_ramvec[i] = trap;
for (i = 33; (i <= 63); i++)
_ramvec[i] = trap;
#endif
for (i = 24; (i <= 30); i++)
_ramvec[i] = inthandler;
#ifndef ENABLE_dBUG
_ramvec[31] = inthandler; // Disables the IRQ7 button
#endif
for (i = 64; (i < 255); i++)
_ramvec[i] = inthandler;
_ramvec[255] = 0;
_ramvec[2] = buserr;
_ramvec[32] = system_call;
}
/***************************************************************************/
volatile unsigned long *icrp;
unsigned int icr;
switch (timer) {
case 2: icr = MCFSIM_ICR2; break;
case 3: icr = MCFSIM_ICR3; break;
case 4: icr = MCFSIM_ICR4; break;
default: icr = MCFSIM_ICR1; break;
}
void coldfire_reset(void)
{
HARD_RESET_NOW();
icrp = (volatile unsigned long *) (MCF_MBAR + icr);
*icrp = (0x8 | level) << ((4 - timer) * 4);
}
/***************************************************************************/
......@@ -164,8 +95,9 @@ void config_BSP(char *commandp, int size)
*pivrp = 0x40;
#endif
#if defined(CONFIG_NETtel) || defined(CONFIG_eLIA) || \
defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
mcf_disableall();
#if defined(CONFIG_NETtel)
/* Copy command line from FLASH to local buffer... */
memcpy(commandp, (char *) 0xf0004000, size);
commandp[size-1] = 0;
......@@ -177,71 +109,13 @@ void config_BSP(char *commandp, int size)
memset(commandp, 0, size);
#endif
mcf_timervector = 69;
mcf_profilevector = 70;
mach_sched_init = coldfire_timer_init;
mach_tick = coldfire_tick;
mach_gettimeoffset = coldfire_timer_offset;
mach_trap_init = coldfire_trap_init;
mach_reset = coldfire_reset;
}
/***************************************************************************/
#ifdef CONFIG_RESETSWITCH
/***************************************************************************/
/*
* Routines to support the NETtel software reset button.
*/
void reset_button(int irq, void *dev_id, struct pt_regs *regs)
{
volatile unsigned long *icrp, *isrp;
extern void flash_eraseconfig(void);
static int inbutton = 0;
/*
* IRQ7 is not maskable by the CPU core. It is possible
* that switch bounce mey get us back here before we have
* really serviced the interrupt.
*/
if (inbutton)
return;
inbutton = 1;
/* Disable interrupt at SIM - best we can do... */
icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
*icrp = (*icrp & 0x07777777) | 0x80000000;
/* Try and de-bounce the switch a little... */
udelay(10000);
flash_eraseconfig();
/* Don't leave here 'till button is no longer pushed! */
isrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ISR);
for (;;) {
if (*isrp & 0x80000000)
break;
}
HARD_RESET_NOW();
/* Should never get here... */
inbutton = 0;
/* Interrupt service done, acknowledge it */
icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
*icrp = (*icrp & 0x07777777) | 0xf0000000;
}
/***************************************************************************/
void reset_setupbutton(void)
{
volatile unsigned long *icrp;
icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
*icrp = (*icrp & 0x07777777) | 0xf0000000;
request_irq(65, reset_button, (SA_INTERRUPT | IRQ_FLG_FAST),
"Reset Button", NULL);
}
/***************************************************************************/
#endif /* CONFIG_RESETSWITCH */
/***************************************************************************/
arch/m68knommu/platform/5307/Makefile
View file @ 162b5250
......@@ -16,7 +16,7 @@ ifdef CONFIG_FULLDEBUG
AFLAGS += -DDEBUGGER_COMPATIBLE_CACHE=1
endif
obj-$(CONFIG_COLDFIRE) += entry.o
obj-$(CONFIG_COLDFIRE) += entry.o timers.o vectors.o
obj-$(CONFIG_M5307) += config.o
ifeq ($(CONFIG_M5307),y)
......
arch/m68knommu/platform/5307/config.c
View file @ 162b5250
......@@ -23,17 +23,19 @@
#include <asm/mcfsim.h>
#include <asm/mcfdma.h>
#include <asm/delay.h>
#if defined(CONFIG_eLIA)
#include <asm/elia.h>
#endif
#include <asm/mcfwdebug.h>
/***************************************************************************/
void reset_setupbutton(void);
void coldfire_profile_init(void);
void coldfire_tick(void);
void coldfire_timer_init(void (*handler)(int, void *, struct pt_regs *));
unsigned long coldfire_timer_offset(void);
void coldfire_trap_init(void);
void coldfire_reset(void);
extern unsigned int mcf_timervector;
extern unsigned int mcf_profilevector;
extern unsigned int mcf_timerlevel;
/***************************************************************************/
......@@ -47,117 +49,7 @@ unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = {
MCF_MBAR + MCFDMA_BASE3,
};
unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
/***************************************************************************/
void coldfire_tick(void)
{
volatile unsigned char *timerp;
/* Reset the ColdFire timer */
timerp = (volatile unsigned char *) (MCF_MBAR + MCFTIMER_BASE1);
timerp[MCFTIMER_TER] = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
}
/***************************************************************************/
void coldfire_timer_init(void (*handler)(int, void *, struct pt_regs *))
{
volatile unsigned short *timerp;
volatile unsigned char *icrp;
/* Set up TIMER 1 as poll clock */
timerp = (volatile unsigned short *) (MCF_MBAR + MCFTIMER_BASE1);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_DISABLE;
timerp[MCFTIMER_TRR] = (unsigned short) ((MCF_CLK / 16) / HZ);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_TIMER1ICR);
#if defined(CONFIG_NETtel) || defined(CONFIG_eLIA) || \
defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3) || \
defined(CONFIG_CLEOPATRA)
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3;
request_irq(30, handler, SA_INTERRUPT, "ColdFire Timer", NULL);
#else
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI3;
request_irq(29, handler, SA_INTERRUPT, "ColdFire Timer", NULL);
#endif
#if defined(CONFIG_NETtel) || defined(CONFIG_eLIA) || \
defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
/* This is not really the right place to do this... */
reset_setupbutton();
#endif
#ifdef CONFIG_HIGHPROFILE
coldfire_profile_init();
#endif
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_TIMER1);
}
/***************************************************************************/
#ifdef CONFIG_HIGHPROFILE
/***************************************************************************/
#define PROFILEHZ 1013
/*
* Use the other timer to provide high accuracy profiling info.
*/
void coldfire_profile_tick(int irq, void *dummy, struct pt_regs *regs)
{
volatile unsigned char *timerp;
/* Reset the ColdFire timer2 */
timerp = (volatile unsigned char *) (MCF_MBAR + MCFTIMER_BASE2);
timerp[MCFTIMER_TER] = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
if (!user_mode(regs)) {
if (prof_buffer && current->pid) {
extern int _stext;
unsigned long ip = instruction_pointer(regs);
ip -= (unsigned long) &_stext;
ip >>= prof_shift;
if (ip < prof_len)
prof_buffer[ip]++;
}
}
}
void coldfire_profile_init(void)
{
volatile unsigned short *timerp;
volatile unsigned char *icrp;
printk("PROFILE: lodging timer2=%d as profile timer\n", PROFILEHZ);
/* Set up TIMER 2 as poll clock */
timerp = (volatile unsigned short *) (MCF_MBAR + MCFTIMER_BASE2);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_DISABLE;
timerp[MCFTIMER_TRR] = (unsigned short) ((MCF_CLK / 16) / PROFILEHZ);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_TIMER2ICR);
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3;
request_irq(31, coldfire_profile_tick, (SA_INTERRUPT | IRQ_FLG_FAST),
"Profile Timer", NULL);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_TIMER2);
}
/***************************************************************************/
#endif /* CONFIG_HIGHPROFILE */
/***************************************************************************/
/*
* Program the vector to be an auto-vectored.
*/
void mcf_autovector(unsigned int vec)
{
......@@ -173,165 +65,57 @@ void mcf_autovector(unsigned int vec)
/***************************************************************************/
extern e_vector *_ramvec;
void set_evector(int vecnum, void (*handler)(void))
{
if (vecnum >= 0 && vecnum <= 255)
_ramvec[vecnum] = handler;
}
/***************************************************************************/
/* assembler routines */
asmlinkage void buserr(void);
asmlinkage void trap(void);
asmlinkage void system_call(void);
asmlinkage void inthandler(void);
#ifdef TRAP_DBG_INTERRUPT
asmlinkage void dbginterrupt(void);
#endif
void __init coldfire_trap_init(void)
{
int i;
#ifndef ENABLE_dBUG
mcf_setimr(MCFSIM_IMR_MASKALL);
#endif
/*
* There is a common trap handler and common interrupt
* handler that handle almost every vector. We treat
* the system call and bus error special, they get their
* own first level handlers.
*/
#ifndef ENABLE_dBUG
for (i = 3; (i <= 23); i++)
_ramvec[i] = trap;
for (i = 33; (i <= 63); i++)
_ramvec[i] = trap;
#endif
#ifdef TRAP_DBG_INTERRUPT
_ramvec[12] = dbginterrupt;
#endif
for (i = 24; (i <= 30); i++)
_ramvec[i] = inthandler;
#ifndef ENABLE_dBUG
_ramvec[31] = inthandler; // Disables the IRQ7 button
#endif
for (i = 64; (i < 255); i++)
_ramvec[i] = inthandler;
_ramvec[255] = 0;
_ramvec[2] = buserr;
_ramvec[32] = system_call;
#ifdef MCF_BDM_DISABLE
/* Disable the BDM clocking. This also turns off most of the rest of
* the BDM device. This is good for EMC reasons. This option is not
* incompatible with the memory protection option.
*/
wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
#endif
}
/***************************************************************************/
#if defined(CONFIG_NETtel) || defined(CONFIG_eLIA) || \
defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
/*
* Routines to support the NETtel software reset button.
*/
void reset_button(int irq, void *dev_id, struct pt_regs *regs)
void mcf_settimericr(unsigned int timer, unsigned int level)
{
extern void flash_eraseconfig(void);
static int inbutton = 0;
/*
* IRQ7 is not maskable by the CPU core. It is possible
* that switch bounce mey get us back here before we have
* really serviced the interrupt.
*/
if (inbutton)
return;
inbutton = 1;
/* Disable interrupt at SIM - best we can do... */
mcf_setimr(mcf_getimr() | MCFSIM_IMR_EINT7);
/* Try and de-bounce the switch a little... */
udelay(10000);
flash_eraseconfig();
/* Don't leave here 'till button is no longer pushed! */
for (;;) {
if ((mcf_getipr() & MCFSIM_IMR_EINT7) == 0)
break;
volatile unsigned char *icrp;
unsigned int icr, imr;
if (timer <= 2) {
switch (timer) {
case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
}
icrp = (volatile unsigned char *) (MCF_MBAR + icr);
*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
mcf_setimr(mcf_getimr() & ~imr);
}
HARD_RESET_NOW();
/* Should never get here... */
inbutton = 0;
/* Interrupt service done, enable it again */
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT7);
}
/***************************************************************************/
void reset_setupbutton(void)
{
volatile unsigned char *mbar;
mbar = (volatile unsigned char *) MCF_MBAR;
*(mbar + MCFSIM_AVR) |= MCFSIM_IMR_EINT7;
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT7);
request_irq(31, reset_button, (SA_INTERRUPT | IRQ_FLG_FAST),
"Reset Button", NULL);
}
#endif /* CONFIG_NETtel || CONFIG_eLIA || CONFIG_DISKtel || CONFIG_SECUREEDGEMP3 */
/***************************************************************************/
void coldfire_reset(void)
{
HARD_RESET_NOW();
}
/***************************************************************************/
void config_BSP(char *commandp, int size)
{
mcf_setimr(MCFSIM_IMR_MASKALL);
#if defined(CONFIG_NETtel) || defined(CONFIG_eLIA) || \
defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3) || \
defined(CONFIG_CLEOPATRA)
/* Copy command line from FLASH to local buffer... */
memcpy(commandp, (char *) 0xf0004000, size);
commandp[size-1] = 0;
/* Different timer setup - to prevent device clash */
mcf_timervector = 30;
mcf_profilevector = 31;
mcf_timerlevel = 6;
#else
memset(commandp, 0, size);
#endif /* CONFIG_NETtel || CONFIG_eLIA || CONFIG_DISKtel || CONFIG_SECUREEDGEMP3 */
#endif
mach_sched_init = coldfire_timer_init;
mach_tick = coldfire_tick;
mach_gettimeoffset = coldfire_timer_offset;
mach_trap_init = coldfire_trap_init;
mach_reset = coldfire_reset;
}
/***************************************************************************/
#ifdef TRAP_DBG_INTERRUPT
asmlinkage void dbginterrupt_c(struct frame *fp)
{
extern void dump(struct pt_regs *fp);
printk("%s(%d): BUS ERROR TRAP\n", __FILE__, __LINE__);
dump((struct pt_regs *) fp);
asm("halt");
#ifdef MCF_BDM_DISABLE
/*
* Disable the BDM clocking. This also turns off most of the rest of
* the BDM device. This is good for EMC reasons. This option is not
* incompatible with the memory protection option.
*/
wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
#endif
}
#endif
/***************************************************************************/
arch/m68knommu/platform/5307/timers.c 0 → 100644
View file @ 162b5250
/***************************************************************************/
/*
* linux/arch/m68knommu/platform/5307/timers.c
*
* Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
*/
/***************************************************************************/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/param.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <asm/irq.h>
#include <asm/traps.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcftimer.h>
#include <asm/mcfsim.h>
/***************************************************************************/
/*
* Default the timer and vector to use for ColdFire. Some ColdFire
* CPU's and some boards may want different. Their sub-architecture
* startup code (in config.c) can change these if they want.
*/
unsigned int mcf_timervector = 29;
unsigned int mcf_profilevector = 31;
unsigned int mcf_timerlevel = 5;
static volatile struct mcftimer *mcf_timerp;
/***************************************************************************/
void coldfire_tick(void)
{
/* Reset the ColdFire timer */
mcf_timerp->ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
}
void coldfire_timer_init(void (*handler)(int, void *, struct pt_regs *))
{
/* Set up an internal TIMER as poll clock */
mcf_timerp = (volatile struct mcftimer *) (MCF_MBAR + MCFTIMER_BASE1);
mcf_timerp->tmr = MCFTIMER_TMR_DISABLE;
mcf_timerp->trr = (unsigned short) ((MCF_BUSCLK / 16) / HZ);
mcf_timerp->tmr = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
request_irq(mcf_timervector, handler, SA_INTERRUPT, "timer", NULL);
mcf_settimericr(1, mcf_timerlevel);
#ifdef CONFIG_HIGHPROFILE
coldfire_profile_init();
#endif
}
/***************************************************************************/
unsigned long coldfire_timer_offset(void)
{
unsigned long trr, tcn;
/* Get the values as longs for accurate calculation. */
tcn = mcf_timerp->tcn;
trr = mcf_timerp->trr;
return((tcn * (1000000 / HZ)) / trr);
}
/***************************************************************************/
#ifdef CONFIG_HIGHPROFILE
/***************************************************************************/
/*
* Choose a reasonably fast profile timer. Make it an odd value to
* try and get good coverage of kernal operations.
*/
#define PROFILEHZ 1013
static volatile struct mcftimer *mcf_proftp;
/*
* Use the other timer to provide high accuracy profiling info.
*/
void coldfire_profile_tick(int irq, void *dummy, struct pt_regs *regs)
{
/* Reset ColdFire timer2 */
mcf_proftp->ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
if (!user_mode(regs)) {
if (prof_buffer && current->pid) {
extern int _stext;
unsigned long ip = instruction_pointer(regs);
ip -= (unsigned long) &_stext;
ip >>= prof_shift;
if (ip < prof_len)
prof_buffer[ip]++;
}
}
}
void coldfire_profile_init(void)
{
printk("PROFILE: lodging TIMER2 @ %dHz as profile timer\n", PROFILEHZ);
/* Set up TIMER 2 as high speed profile clock */
mcf_proftp = (volatile struct mcftimer *) (MCF_MBAR + MCFTIMER_BASE2);
mcf_proftp->tmr = MCFTIMER_TMR_DISABLE;
mcf_proftp->trr = (unsigned short) ((MCF_CLK / 16) / PROFILEHZ);
mcf_proftp->tmr = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
request_irq(mcf_profilevector, coldfire_profile_tick,
(SA_INTERRUPT | IRQ_FLG_FAST), "profile timer", NULL);
mcf_settimericr(2, 7);
}
/***************************************************************************/
#endif /* CONFIG_HIGHPROFILE */
/***************************************************************************/
arch/m68knommu/platform/5407/config.c
View file @ 162b5250
......@@ -26,7 +26,15 @@
/***************************************************************************/
void coldfire_profile_init(void);
void coldfire_tick(void);
void coldfire_timer_init(void (*handler)(int, void *, struct pt_regs *));
unsigned long coldfire_timer_offset(void);
void coldfire_trap_init(void);
void coldfire_reset(void);
extern unsigned int mcf_timervector;
extern unsigned int mcf_profilevector;
extern unsigned int mcf_timerlevel;
/***************************************************************************/
......@@ -40,110 +48,7 @@ unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = {
MCF_MBAR + MCFDMA_BASE3,
};
unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
/***************************************************************************/
void coldfire_tick(void)
{
volatile unsigned char *timerp;
/* Reset the ColdFire timer */
timerp = (volatile unsigned char *) (MCF_MBAR + MCFTIMER_BASE1);
timerp[MCFTIMER_TER] = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
}
/***************************************************************************/
void coldfire_timer_init(void (*handler)(int, void *, struct pt_regs *))
{
volatile unsigned short *timerp;
volatile unsigned char *icrp;
/* Set up TIMER 1 as poll clock */
timerp = (volatile unsigned short *) (MCF_MBAR + MCFTIMER_BASE1);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_DISABLE;
timerp[MCFTIMER_TRR] = (unsigned short) ((MCF_CLK / 16) / HZ);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_TIMER1ICR);
#if defined(CONFIG_CLEOPATRA)
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3;
request_irq(30, handler, SA_INTERRUPT, "ColdFire Timer", NULL);
#else
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI3;
request_irq(29, handler, SA_INTERRUPT, "ColdFire Timer", NULL);
#endif
#ifdef CONFIG_HIGHPROFILE
coldfire_profile_init();
#endif
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_TIMER1);
}
/***************************************************************************/
#ifdef CONFIG_HIGHPROFILE
/***************************************************************************/
#define PROFILEHZ 1013
/*
* Use the other timer to provide high accuracy profiling info.
*/
void coldfire_profile_tick(int irq, void *dummy, struct pt_regs *regs)
{
volatile unsigned char *timerp;
/* Reset the ColdFire timer2 */
timerp = (volatile unsigned char *) (MCF_MBAR + MCFTIMER_BASE2);
timerp[MCFTIMER_TER] = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
if (!user_mode(regs)) {
if (prof_buffer && current->pid) {
extern int _stext;
unsigned long ip = instruction_pointer(regs);
ip -= (unsigned long) &_stext;
ip >>= prof_shift;
if (ip < prof_len)
prof_buffer[ip]++;
}
}
}
void coldfire_profile_init(void)
{
volatile unsigned short *timerp;
volatile unsigned char *icrp;
printk("PROFILE: lodging timer2=%d as profile timer\n", PROFILEHZ);
/* Set up TIMER 2 as poll clock */
timerp = (volatile unsigned short *) (MCF_MBAR + MCFTIMER_BASE2);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_DISABLE;
timerp[MCFTIMER_TRR] = (unsigned short) ((MCF_CLK / 16) / PROFILEHZ);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_TIMER2ICR);
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3;
request_irq(31, coldfire_profile_tick, (SA_INTERRUPT | IRQ_FLG_FAST),
"Profile Timer", NULL);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_TIMER2);
}
/***************************************************************************/
#endif /* CONFIG_HIGHPROFILE */
/***************************************************************************/
/*
* Program the vector to be an auto-vectored.
*/
void mcf_autovector(unsigned int vec)
{
......@@ -159,78 +64,42 @@ void mcf_autovector(unsigned int vec)
/***************************************************************************/
extern e_vector *_ramvec;
void set_evector(int vecnum, void (*handler)(void))
void mcf_settimericr(unsigned int timer, unsigned int level)
{
if (vecnum >= 0 && vecnum <= 255)
_ramvec[vecnum] = handler;
volatile unsigned char *icrp;
unsigned int icr, imr;
if (timer <= 2) {
switch (timer) {
case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
}
icrp = (volatile unsigned char *) (MCF_MBAR + icr);
*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
mcf_setimr(mcf_getimr() & ~imr);
}
}
/***************************************************************************/
/* assembler routines */
asmlinkage void buserr(void);
asmlinkage void trap(void);
asmlinkage void system_call(void);
asmlinkage void inthandler(void);
void __init coldfire_trap_init(void)
void config_BSP(char *commandp, int size)
{
int i;
#ifndef ENABLE_dBUG
mcf_setimr(MCFSIM_IMR_MASKALL);
#endif
/*
* There is a common trap handler and common interrupt
* handler that handle almost every vector. We treat
* the system call and bus error special, they get their
* own first level handlers.
*/
#ifndef ENABLE_dBUG
for (i = 3; (i <= 23); i++)
_ramvec[i] = trap;
for (i = 33; (i <= 63); i++)
_ramvec[i] = trap;
#endif
memset(commandp, 0, size);
for (i = 24; (i <= 30); i++)
_ramvec[i] = inthandler;
#ifndef ENABLE_dBUG
_ramvec[31] = inthandler; // Disables the IRQ7 button
#if defined(CONFIG_CLEOPATRA)
/* Different timer setup - to prevent device clash */
mcf_timervector = 30;
mcf_profilevector = 31;
mcf_timerlevel = 6;
#endif
for (i = 64; (i < 255); i++)
_ramvec[i] = inthandler;
_ramvec[255] = 0;
_ramvec[2] = buserr;
_ramvec[32] = system_call;
}
/***************************************************************************/
void config_BSP(char *commandp, int size)
{
memset(commandp, 0, size);
mach_sched_init = coldfire_timer_init;
mach_tick = coldfire_tick;
mach_gettimeoffset = coldfire_timer_offset;
mach_trap_init = coldfire_trap_init;
mach_reset = coldfire_reset;
}
/***************************************************************************/
#ifdef TRAP_DBG_INTERRUPT
asmlinkage void dbginterrupt_c(struct frame *fp)
{
extern void dump(struct pt_regs *fp);
printk("%s(%d): BUS ERROR TRAP\n", __FILE__, __LINE__);
dump((struct pt_regs *) fp);
asm("halt");
}
#endif
/***************************************************************************/
arch/m68knommu/platform/68328/entry.S
View file @ 162b5250
......@@ -14,6 +14,7 @@
#include <linux/sys.h>
#include <linux/linkage.h>
#include <asm/thread_info.h>
#include <asm/unistd.h>
#include <asm/errno.h>
#include <asm/setup.h>
#include <asm/segment.h>
......
arch/m68knommu/platform/68328/ints.c
View file @ 162b5250
......@@ -13,6 +13,7 @@
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <linux/errno.h>
#include <asm/system.h>
#include <asm/irq.h>
......
arch/m68knommu/platform/68360/commproc.c
View file @ 162b5250
......@@ -71,7 +71,7 @@ static void cpm_interrupt(int irq, void * dev, struct pt_regs * regs);
static void cpm_error_interrupt(void *);
/* prototypes: */
void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
void cpm_install_handler(int vec, void (*handler)(), void *dev_id);
void m360_cpm_reset(void);
......@@ -207,7 +207,7 @@ cpm_error_interrupt(void *dev)
/* Install a CPM interrupt handler.
*/
void
cpm_install_handler(int vec, void (*handler)(void *), void *dev_id)
cpm_install_handler(int vec, void (*handler)(), void *dev_id)
{
request_irq(vec, handler, IRQ_FLG_LOCK, "timer", dev_id);
......
arch/m68knommu/platform/68360/entry.S
View file @ 162b5250
......@@ -16,6 +16,7 @@
#include <linux/sys.h>
#include <linux/linkage.h>
#include <asm/thread_info.h>
#include <asm/unistd.h>
#include <asm/errno.h>
#include <asm/setup.h>
#include <asm/segment.h>
......
arch/m68knommu/platform/68360/ints.c
View file @ 162b5250
......@@ -15,6 +15,7 @@
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <linux/errno.h>
#include <asm/system.h>
#include <asm/irq.h>
......
arch/m68knommu/platform/68VZ328/Makefile
View file @ 162b5250
......@@ -2,11 +2,5 @@
# Makefile for arch/m68knommu/platform/68VZ328.
#
obj-y := $(BOARD)/config.o
EXTRA_TARGETS := $(BOARD)/bootlogo.rh $(BOARD)/crt0_$(MODEL).o
$(obj)/$(BOARD)/bootlogo.rh: $(src)/../68EZ328/bootlogo.h
perl $(src)/../68328/bootlogo.pl < $(src)/../68EZ328/bootlogo.h \
> $(obj)/$(BOARD)/bootlogo.rh
obj-y := $(BOARD)/
arch/m68knommu/platform/68VZ328/de2/Makefile 0 → 100644
View file @ 162b5250
#
# Makefile for arch/m68knommu/platform/68VZ328/de2.
#
obj-y := config.o
EXTRA_TARGETS := bootlogo.rh crt0_$(MODEL).o
$(obj)/bootlogo.rh: $(src)/../../68EZ328/bootlogo.h
perl $(src)/../../68328/bootlogo.pl < $(src)/../../68EZ328/bootlogo.h \
> $(obj)/bootlogo.rh
arch/m68knommu/platform/68VZ328/de2/config.c
View file @ 162b5250
......@@ -147,5 +147,5 @@ void config_BSP(char *command, int len)
mach_reset = dragen2_reset;
mach_gettod = dragen2_gettod;
config_M68VZ328_irq();
config_M68328_irq();
}
arch/m68knommu/platform/68VZ328/ucdimm/Makefile 0 → 100644
View file @ 162b5250
#
# Makefile for arch/m68knommu/platform/68VZ328/ucdimm.
#
obj-y := config.o
EXTRA_TARGETS := bootlogo.rh crt0_$(MODEL).o
$(obj)/bootlogo.rh: $(src)/../../68EZ328/bootlogo.h
perl $(src)/../../68328/bootlogo.pl < $(src)/../../68EZ328/bootlogo.h \
> $(obj)/bootlogo.rh
arch/m68knommu/platform/68VZ328/ucdimm/config.c
View file @ 162b5250
......@@ -115,5 +115,5 @@ void config_BSP(char *command, int len)
mach_gettod = BSP_gettod;
mach_reset = BSP_reset;
config_M68VZ328_irq();
config_M68328_irq();
}
arch/parisc/kernel/sys_parisc32.c
View file @ 162b5250
......@@ -316,35 +316,6 @@ asmlinkage long sys32_unimplemented(int r26, int r25, int r24, int r23,
return -ENOSYS;
}
extern asmlinkage long sys_fcntl(unsigned int fd, unsigned int cmd, unsigned long arg);
asmlinkage long sys32_fcntl(unsigned int fd, unsigned int cmd, unsigned long arg)
{
switch (cmd) {
case F_GETLK:
case F_SETLK:
case F_SETLKW:
{
struct flock f;
long ret;
if (get_compat_flock(&f, (struct compat_flock *)arg))
return -EFAULT;
KERNEL_SYSCALL(ret, sys_fcntl, fd, cmd, (unsigned long)&f);
if (ret) return ret;
if (f.l_start >= 0x7fffffffUL ||
f.l_len >= 0x7fffffffUL ||
f.l_start + f.l_len >= 0x7fffffffUL)
return -EOVERFLOW;
if (put_compat_flock(&f, (struct compat_flock *)arg))
return -EFAULT;
return 0;
}
default:
return sys_fcntl(fd, cmd, (unsigned long)arg);
}
}
#ifdef CONFIG_SYSCTL
struct __sysctl_args32 {
......@@ -1300,28 +1271,6 @@ asmlinkage long sys32_msgrcv(int msqid,
return err;
}
/* LFS */
extern asmlinkage long sys_fcntl(unsigned int, unsigned int, unsigned long);
asmlinkage long sys32_fcntl64(unsigned int fd, unsigned int cmd, unsigned long arg)
{
switch (cmd) {
case F_GETLK64:
cmd = F_GETLK;
break;
case F_SETLK64:
cmd = F_SETLK;
break;
case F_SETLKW64:
cmd = F_SETLKW;
break;
default:
break;
}
return sys32_fcntl(fd, cmd, arg);
}
/* EXPORT/UNEXPORT */
struct nfsctl_export32 {
char ex_client[NFSCLNT_IDMAX+1];
......
arch/parisc/kernel/syscall.S
View file @ 162b5250
......@@ -409,8 +409,7 @@ sys_call_table:
ENTRY_SAME(getpeername)
/* This one's a huge ugly mess */
ENTRY_DIFF(ioctl)
/* struct flock? */
ENTRY_DIFF(fcntl) /* 55 */
ENTRY_COMP(fcntl) /* 55 */
ENTRY_SAME(socketpair)
ENTRY_SAME(setpgid)
ENTRY_SAME(send)
......@@ -589,7 +588,7 @@ sys_call_table:
ENTRY_OURS(truncate64)
ENTRY_OURS(ftruncate64) /* 200 */
ENTRY_SAME(getdents64)
ENTRY_DIFF(fcntl64)
ENTRY_COMP(fcntl64)
ENTRY_SAME(ni_syscall)
ENTRY_SAME(ni_syscall)
ENTRY_SAME(ni_syscall) /* 205 */
......
arch/s390x/kernel/entry.S
View file @ 162b5250
......@@ -452,7 +452,7 @@ sys_call_table:
.long SYSCALL(sys_umount,sys32_umount_wrapper)
.long SYSCALL(sys_ni_syscall,sys_ni_syscall) /* old lock syscall */
.long SYSCALL(sys_ioctl,sys32_ioctl_wrapper)
.long SYSCALL(sys_fcntl,sys32_fcntl_wrapper) /* 55 */
.long SYSCALL(sys_fcntl,compat_sys_fcntl_wrapper) /* 55 */
.long SYSCALL(sys_ni_syscall,sys_ni_syscall) /* intel mpx syscall */
.long SYSCALL(sys_setpgid,sys32_setpgid_wrapper)
.long SYSCALL(sys_ni_syscall,sys_ni_syscall) /* old ulimit syscall */
......@@ -618,7 +618,7 @@ sys_call_table:
.long SYSCALL(sys_mincore,sys32_mincore_wrapper)
.long SYSCALL(sys_madvise,sys32_madvise_wrapper)
.long SYSCALL(sys_getdents64,sys32_getdents64_wrapper)/* 220 */
.long SYSCALL(sys_ni_syscall,sys32_fcntl64_wrapper)
.long SYSCALL(sys_ni_syscall,compat_sys_fcntl64_wrapper)
.long SYSCALL(sys_readahead,sys32_readahead)
.long SYSCALL(sys_ni_syscall,sys32_sendfile64)
.long SYSCALL(sys_setxattr,sys32_setxattr_wrapper)
......
arch/s390x/kernel/linux32.c
View file @ 162b5250
......@@ -834,57 +834,6 @@ asmlinkage int sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u
return err;
}
extern asmlinkage long sys_fcntl(unsigned int fd, unsigned int cmd, unsigned long arg);
asmlinkage long sys32_fcntl(unsigned int fd, unsigned int cmd, unsigned long arg)
{
switch (cmd) {
case F_GETLK:
{
struct flock f;
mm_segment_t old_fs;
long ret;
if(get_compat_flock(&f, (struct compat_flock *)A(arg)))
return -EFAULT;
old_fs = get_fs(); set_fs (KERNEL_DS);
ret = sys_fcntl(fd, cmd, (unsigned long)&f);
set_fs (old_fs);
if (ret) return ret;
if (f.l_start >= 0x7fffffffUL ||
f.l_start + f.l_len >= 0x7fffffffUL)
return -EOVERFLOW;
if(put_compat_flock(&f, (struct compat_flock *)A(arg)))
return -EFAULT;
return 0;
}
case F_SETLK:
case F_SETLKW:
{
struct flock f;
mm_segment_t old_fs;
long ret;
if(get_compat_flock(&f, (struct compat_flock *)A(arg)))
return -EFAULT;
old_fs = get_fs(); set_fs (KERNEL_DS);
ret = sys_fcntl(fd, cmd, (unsigned long)&f);
set_fs (old_fs);
if (ret) return ret;
return 0;
}
default:
return sys_fcntl(fd, cmd, (unsigned long)arg);
}
}
asmlinkage long sys32_fcntl64(unsigned int fd, unsigned int cmd, unsigned long arg)
{
if (cmd >= F_GETLK64 && cmd <= F_SETLKW64)
return sys_fcntl(fd, cmd + F_GETLK - F_GETLK64, arg);
return sys32_fcntl(fd, cmd, arg);
}
extern asmlinkage long sys_truncate(const char * path, unsigned long length);
extern asmlinkage long sys_ftruncate(unsigned int fd, unsigned long length);
......
arch/s390x/kernel/linux32.h
View file @ 162b5250
......@@ -21,10 +21,6 @@ struct ipc_kludge_32 {
__s32 msgtyp;
};
#define F_GETLK64 12
#define F_SETLK64 13
#define F_SETLKW64 14
struct old_sigaction32 {
__u32 sa_handler; /* Really a pointer, but need to deal with 32 bits */
compat_old_sigset_t sa_mask; /* A 32 bit mask */
......
arch/s390x/kernel/wrapper32.S
View file @ 162b5250
......@@ -227,12 +227,12 @@ sys32_ioctl_wrapper:
llgfr %r4,%r4 # unsigned int
jg sys32_ioctl # branch to system call
.globl sys32_fcntl_wrapper
sys32_fcntl_wrapper:
.globl compat_sys_fcntl_wrapper
compat_sys_fcntl_wrapper:
llgfr %r2,%r2 # unsigned int
llgfr %r3,%r3 # unsigned int
llgfr %r4,%r4 # unsigned long
jg sys32_fcntl # branch to system call
jg compat_sys_fcntl # branch to system call
.globl sys32_setpgid_wrapper
sys32_setpgid_wrapper:
......@@ -1050,12 +1050,12 @@ sys32_getdents64_wrapper:
llgfr %r4,%r4 # unsigned int
jg sys_getdents64 # branch to system call
.globl sys32_fcntl64_wrapper
sys32_fcntl64_wrapper:
.globl compat_sys_fcntl64_wrapper
compat_sys_fcntl64_wrapper:
llgfr %r2,%r2 # unsigned int
llgfr %r3,%r3 # unsigned int
llgfr %r4,%r4 # unsigned long
jg sys32_fcntl64 # branch to system call
jg compat_sys_fcntl64 # branch to system call
.globl sys32_stat64_wrapper
sys32_stat64_wrapper:
......
arch/x86_64/boot/Makefile
View file @ 162b5250
......@@ -62,33 +62,33 @@ $(obj)/compressed/vmlinux: FORCE
# Set this if you want to pass append arguments to the zdisk/fdimage kernel
FDARGS =
$(obj)/mtools.conf: $(obj)/mtools.conf.in
$(obj)/mtools.conf: $(src)/mtools.conf.in
sed -e 's|@OBJ@|$(obj)|g' < $< > $@
# This requires write access to /dev/fd0
zdisk: $(BOOTIMAGE) $(obj)/mtools.conf
MTOOLSRC=$(src)/mtools.conf mformat a: ; sync
MTOOLSRC=$(obj)/mtools.conf mformat a: ; sync
syslinux /dev/fd0 ; sync
echo 'default linux $(FDARGS)' | \
MTOOLSRC=$(src)/mtools.conf mcopy - a:syslinux.cfg
MTOOLSRC=$(src)/mtools.conf mcopy $(BOOTIMAGE) a:linux ; sync
MTOOLSRC=$(obj)/mtools.conf mcopy - a:syslinux.cfg
MTOOLSRC=$(obj)/mtools.conf mcopy $(BOOTIMAGE) a:linux ; sync
# These require being root or having syslinux 2.02 or higher installed
fdimage fdimage144: $(BOOTIMAGE) $(src)/mtools.conf
fdimage fdimage144: $(BOOTIMAGE) $(obj)/mtools.conf
dd if=/dev/zero of=$(obj)/fdimage bs=1024 count=1440
MTOOLSRC=$(src)/mtools.conf mformat v: ; sync
MTOOLSRC=$(obj)/mtools.conf mformat v: ; sync
syslinux $(obj)/fdimage ; sync
echo 'default linux $(FDARGS)' | \
MTOOLSRC=$(src)/mtools.conf mcopy - v:syslinux.cfg
MTOOLSRC=$(src)/mtools.conf mcopy $(BOOTIMAGE) v:linux ; sync
MTOOLSRC=$(obj)/mtools.conf mcopy - v:syslinux.cfg
MTOOLSRC=$(obj)/mtools.conf mcopy $(BOOTIMAGE) v:linux ; sync
fdimage288: $(BOOTIMAGE) $(src)/mtools.conf
fdimage288: $(BOOTIMAGE) $(obj)/mtools.conf
dd if=/dev/zero of=$(obj)/fdimage bs=1024 count=2880
MTOOLSRC=$(src)/mtools.conf mformat w: ; sync
MTOOLSRC=$(obj)/mtools.conf mformat w: ; sync
syslinux $(obj)/fdimage ; sync
echo 'default linux $(FDARGS)' | \
MTOOLSRC=$(src)/mtools.conf mcopy - w:syslinux.cfg
MTOOLSRC=$(src)/mtools.conf mcopy $(BOOTIMAGE) w:linux ; sync
MTOOLSRC=$(obj)/mtools.conf mcopy - w:syslinux.cfg
MTOOLSRC=$(obj)/mtools.conf mcopy $(BOOTIMAGE) w:linux ; sync
zlilo: $(BOOTIMAGE)
if [ -f $(INSTALL_PATH)/vmlinuz ]; then mv $(INSTALL_PATH)/vmlinuz $(INSTALL_PATH)/vmlinuz.old; fi
......
arch/x86_64/boot/setup.S
View file @ 162b5250
......@@ -829,13 +829,6 @@ gdt:
.word 0x9200 # data read/write
.word 0x00CF # granularity = 4096, 386
# (+5th nibble of limit)
# this is 64bit descriptor for code
.word 0xFFFF
.word 0
.word 0x9A00 # code read/exec
.word 0x00AF # as above, but it is long mode and with D=0
# it does not seem to do the trick.
idt_48:
.word 0 # idt limit = 0
.word 0, 0 # idt base = 0L
......
arch/x86_64/ia32/Makefile
View file @ 162b5250
......@@ -3,5 +3,5 @@
#
obj-$(CONFIG_IA32_EMULATION) := ia32entry.o sys_ia32.o ia32_ioctl.o \
ia32_signal.o \
ia32_signal.o tls32.o \
ia32_binfmt.o fpu32.o ptrace32.o ipc32.o syscall32.o
arch/x86_64/ia32/ia32_signal.c
View file @ 162b5250
......@@ -106,20 +106,24 @@ sys32_sigaltstack(const stack_ia32_t *uss_ptr, stack_ia32_t *uoss_ptr,
stack_t uss,uoss;
int ret;
mm_segment_t seg;
if (uss_ptr) {
u32 ptr;
if (!access_ok(VERIFY_READ,uss_ptr,sizeof(stack_ia32_t)) ||
__get_user(ptr_to_u32(uss.ss_sp), &uss_ptr->ss_sp) ||
__get_user((u32)uss.ss_flags, &uss_ptr->ss_flags) ||
__get_user((u32)uss.ss_size, &uss_ptr->ss_size))
__get_user(ptr, &uss_ptr->ss_sp) ||
__get_user(uss.ss_flags, &uss_ptr->ss_flags) ||
__get_user(uss.ss_size, &uss_ptr->ss_size))
return -EFAULT;
uss.ss_sp = (void *)(u64)ptr;
}
seg = get_fs();
set_fs(KERNEL_DS);
ret = do_sigaltstack(&uss, &uoss, regs.rsp);
ret = do_sigaltstack(uss_ptr ? &uss : NULL, &uoss, regs.rsp);
set_fs(seg);
if (ret >= 0 && uoss_ptr) {
if (!access_ok(VERIFY_WRITE,uss_ptr,sizeof(stack_ia32_t)) ||
__put_user(ptr_to_u32(uss.ss_sp), &uss_ptr->ss_sp) ||
__put_user((u32)uss.ss_flags, &uss_ptr->ss_flags) ||
__put_user((u32)uss.ss_size, &uss_ptr->ss_size))
if (!access_ok(VERIFY_WRITE,uoss_ptr,sizeof(stack_ia32_t)) ||
__put_user((u32)(u64)uss.ss_sp, &uoss_ptr->ss_sp) ||
__put_user(uss.ss_flags, &uoss_ptr->ss_flags) ||
__put_user(uss.ss_size, &uoss_ptr->ss_size))
ret = -EFAULT;
}
return ret;
......
arch/x86_64/ia32/ia32entry.S
View file @ 162b5250
......@@ -255,7 +255,7 @@ ia32_sys_call_table:
.quad sys_umount /* new_umount */
.quad ni_syscall /* old lock syscall holder */
.quad sys32_ioctl
.quad sys32_fcntl64 /* 55 */
.quad compat_sys_fcntl64 /* 55 */
.quad ni_syscall /* old mpx syscall holder */
.quad sys_setpgid
.quad ni_syscall /* old ulimit syscall holder */
......@@ -421,7 +421,7 @@ ia32_sys_call_table:
.quad sys_mincore
.quad sys_madvise
.quad sys_getdents64 /* 220 getdents64 */
.quad sys32_fcntl64
.quad compat_sys_fcntl64
.quad sys_ni_syscall /* tux */
.quad sys_ni_syscall /* security */
.quad sys_gettid
......@@ -443,8 +443,8 @@ ia32_sys_call_table:
.quad compat_sys_futex /* 240 */
.quad sys32_sched_setaffinity
.quad sys32_sched_getaffinity
.quad sys_set_thread_area
.quad sys_get_thread_area
.quad sys32_set_thread_area
.quad sys32_get_thread_area
.quad sys32_io_setup
.quad sys_io_destroy
.quad sys32_io_getevents
......
arch/x86_64/ia32/ptrace32.c
View file @ 162b5250
......@@ -22,6 +22,8 @@
#include <asm/errno.h>
#include <asm/debugreg.h>
#include <asm/i387.h>
#include <asm/desc.h>
#include <asm/ldt.h>
#include <asm/fpu32.h>
#include <linux/mm.h>
#include <linux/ptrace.h>
......
arch/x86_64/ia32/sys_ia32.c
View file @ 162b5250
......@@ -1016,102 +1016,6 @@ sys32_getrusage(int who, struct rusage32 *ru)
return ret;
}
extern asmlinkage long sys_fcntl(unsigned int fd, unsigned int cmd, unsigned long arg);
asmlinkage long sys32_fcntl64(unsigned int fd, unsigned int cmd, unsigned long arg);
asmlinkage long sys32_fcntl(unsigned int fd, unsigned int cmd, unsigned long arg)
{
switch (cmd) {
case F_GETLK:
case F_SETLK:
case F_SETLKW:
{
struct flock f;
mm_segment_t old_fs;
long ret;
if (get_compat_flock(&f, (struct compat_flock *)arg))
return -EFAULT;
old_fs = get_fs(); set_fs (KERNEL_DS);
ret = sys_fcntl(fd, cmd, (unsigned long)&f);
set_fs (old_fs);
if (ret) return ret;
if (put_compat_flock(&f, (struct compat_flock *)arg))
return -EFAULT;
return 0;
}
case F_GETLK64:
case F_SETLK64:
case F_SETLKW64:
return sys32_fcntl64(fd,cmd,arg);
default:
return sys_fcntl(fd, cmd, (unsigned long)arg);
}
}
static inline int get_flock64(struct ia32_flock64 *fl32, struct flock *fl64)
{
if (access_ok(fl32, sizeof(struct ia32_flock64), VERIFY_WRITE)) {
int ret = __get_user(fl64->l_type, &fl32->l_type);
ret |= __get_user(fl64->l_whence, &fl32->l_whence);
ret |= __get_user(fl64->l_start, &fl32->l_start);
ret |= __get_user(fl64->l_len, &fl32->l_len);
ret |= __get_user(fl64->l_pid, &fl32->l_pid);
return ret;
}
return -EFAULT;
}
static inline int put_flock64(struct ia32_flock64 *fl32, struct flock *fl64)
{
if (access_ok(fl32, sizeof(struct ia32_flock64), VERIFY_WRITE)) {
int ret = __put_user(fl64->l_type, &fl32->l_type);
ret |= __put_user(fl64->l_whence, &fl32->l_whence);
ret |= __put_user(fl64->l_start, &fl32->l_start);
ret |= __put_user(fl64->l_len, &fl32->l_len);
ret |= __put_user(fl64->l_pid, &fl32->l_pid);
return ret;
}
return -EFAULT;
}
asmlinkage long sys32_fcntl64(unsigned int fd, unsigned int cmd, unsigned long arg)
{
struct flock fl64;
mm_segment_t oldfs = get_fs();
int ret = 0;
int oldcmd = cmd;
unsigned long oldarg = arg;
switch (cmd) {
case F_GETLK64:
cmd = F_GETLK;
goto cnv;
case F_SETLK64:
cmd = F_SETLK;
goto cnv;
case F_SETLKW64:
cmd = F_SETLKW;
cnv:
ret = get_flock64((struct ia32_flock64 *)arg, &fl64);
arg = (unsigned long)&fl64;
set_fs(KERNEL_DS);
break;
case F_GETLK:
case F_SETLK:
case F_SETLKW:
return sys32_fcntl(fd,cmd,arg);
}
if (!ret)
ret = sys_fcntl(fd, cmd, arg);
set_fs(oldfs);
if (oldcmd == F_GETLK64 && !ret)
ret = put_flock64((struct ia32_flock64 *)oldarg, &fl64);
return ret;
}
int sys32_ni_syscall(int call)
{
printk(KERN_INFO "IA32 syscall %d from %s not implemented\n", call,
......@@ -1261,8 +1165,8 @@ siginfo64to32(siginfo_t32 *d, siginfo_t *s)
if (s->si_signo >= SIGRTMIN) {
d->si_pid = s->si_pid;
d->si_uid = s->si_uid;
/* XXX: Ouch, how to find this out??? */
d->si_int = s->si_int;
memcpy(&d->si_int, &s->si_int,
sizeof(siginfo_t) - offsetof(siginfo_t,si_int));
} else switch (s->si_signo) {
/* XXX: What about POSIX1.b timers */
case SIGCHLD:
......@@ -1299,8 +1203,9 @@ siginfo32to64(siginfo_t *d, siginfo_t32 *s)
if (s->si_signo >= SIGRTMIN) {
d->si_pid = s->si_pid;
d->si_uid = s->si_uid;
/* XXX: Ouch, how to find this out??? */
d->si_int = s->si_int;
memcpy(&d->si_int,
&s->si_int,
sizeof(siginfo_t) - offsetof(siginfo_t, si_int));
} else switch (s->si_signo) {
/* XXX: What about POSIX1.b timers */
case SIGCHLD:
......
arch/x86_64/ia32/tls32.c 0 → 100644
View file @ 162b5250
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/user.h>
#include <asm/uaccess.h>
#include <asm/desc.h>
#include <asm/system.h>
#include <asm/ldt.h>
#include <asm/processor.h>
#include <asm/proto.h>
/*
* sys_alloc_thread_area: get a yet unused TLS descriptor index.
*/
static int get_free_idx(void)
{
struct thread_struct *t = &current->thread;
int idx;
for (idx = 0; idx < GDT_ENTRY_TLS_ENTRIES; idx++)
if (desc_empty((struct n_desc_struct *)(t->tls_array) + idx))
return idx + GDT_ENTRY_TLS_MIN;
return -ESRCH;
}
/*
* Set a given TLS descriptor:
* When you want addresses > 32bit use arch_prctl()
*/
int do_set_thread_area(struct thread_struct *t, struct user_desc *u_info)
{
struct user_desc info;
struct n_desc_struct *desc;
int cpu, idx;
if (copy_from_user(&info, u_info, sizeof(info)))
return -EFAULT;
idx = info.entry_number;
/*
* index -1 means the kernel should try to find and
* allocate an empty descriptor:
*/
if (idx == -1) {
idx = get_free_idx();
if (idx < 0)
return idx;
if (put_user(idx, &u_info->entry_number))
return -EFAULT;
}
if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX)
return -EINVAL;
desc = ((struct n_desc_struct *)t->tls_array) + idx - GDT_ENTRY_TLS_MIN;
/*
* We must not get preempted while modifying the TLS.
*/
cpu = get_cpu();
if (LDT_empty(&info)) {
desc->a = 0;
desc->b = 0;
} else {
desc->a = LDT_entry_a(&info);
desc->b = LDT_entry_b(&info);
}
if (t == &current->thread)
load_TLS(t, cpu);
put_cpu();
return 0;
}
asmlinkage long sys32_set_thread_area(struct user_desc *u_info)
{
return do_set_thread_area(&current->thread, u_info);
}
/*
* Get the current Thread-Local Storage area:
*/
#define GET_BASE(desc) ( \
(((desc)->a >> 16) & 0x0000ffff) | \
(((desc)->b << 16) & 0x00ff0000) | \
( (desc)->b & 0xff000000) )
#define GET_LIMIT(desc) ( \
((desc)->a & 0x0ffff) | \
((desc)->b & 0xf0000) )
#define GET_32BIT(desc) (((desc)->b >> 23) & 1)
#define GET_CONTENTS(desc) (((desc)->b >> 10) & 3)
#define GET_WRITABLE(desc) (((desc)->b >> 9) & 1)
#define GET_LIMIT_PAGES(desc) (((desc)->b >> 23) & 1)
#define GET_PRESENT(desc) (((desc)->b >> 15) & 1)
#define GET_USEABLE(desc) (((desc)->b >> 20) & 1)
#define GET_LONGMODE(desc) (((desc)->b >> 21) & 1)
int do_get_thread_area(struct thread_struct *t, struct user_desc *u_info)
{
struct user_desc info;
struct n_desc_struct *desc;
int idx;
if (get_user(idx, &u_info->entry_number))
return -EFAULT;
if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX)
return -EINVAL;
desc = ((struct n_desc_struct *)t->tls_array) + idx - GDT_ENTRY_TLS_MIN;
memset(&info, 0, sizeof(struct user_desc));
info.entry_number = idx;
info.base_addr = GET_BASE(desc);
info.limit = GET_LIMIT(desc);
info.seg_32bit = GET_32BIT(desc);
info.contents = GET_CONTENTS(desc);
info.read_exec_only = !GET_WRITABLE(desc);
info.limit_in_pages = GET_LIMIT_PAGES(desc);
info.seg_not_present = !GET_PRESENT(desc);
info.useable = GET_USEABLE(desc);
info.lm = GET_LONGMODE(desc);
if (copy_to_user(u_info, &info, sizeof(info)))
return -EFAULT;
return 0;
}
asmlinkage long sys32_get_thread_area(struct user_desc *u_info)
{
return do_get_thread_area(&current->thread, u_info);
}
int ia32_child_tls(struct task_struct *p, struct pt_regs *childregs)
{
struct n_desc_struct *desc;
struct user_desc info, *cp;
int idx;
cp = (void *)childregs->rsi;
if (copy_from_user(&info, cp, sizeof(info)))
return -EFAULT;
if (LDT_empty(&info))
return -EINVAL;
idx = info.entry_number;
if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX)
return -EINVAL;
desc = (struct n_desc_struct *)(p->thread.tls_array) + idx - GDT_ENTRY_TLS_MIN;
desc->a = LDT_entry_a(&info);
desc->b = LDT_entry_b(&info);
return 0;
}
arch/x86_64/kernel/apic.c
View file @ 162b5250
......@@ -981,9 +981,6 @@ void smp_apic_timer_interrupt(struct pt_regs *regs)
asmlinkage void smp_spurious_interrupt(void)
{
unsigned int v;
static unsigned long last_warning;
static unsigned long skipped;
irq_enter();
/*
* Check if this really is a spurious interrupt and ACK it
......@@ -994,8 +991,12 @@ asmlinkage void smp_spurious_interrupt(void)
if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
ack_APIC_irq();
#if 0
static unsigned long last_warning;
static unsigned long skipped;
/* see sw-dev-man vol 3, chapter 7.4.13.5 */
if (last_warning+30*HZ < jiffies) {
if (time_before(last_warning+30*HZ,jiffies)) {
printk(KERN_INFO "spurious APIC interrupt on CPU#%d, %ld skipped.\n",
smp_processor_id(), skipped);
last_warning = jiffies;
......@@ -1003,6 +1004,7 @@ asmlinkage void smp_spurious_interrupt(void)
} else {
skipped++;
}
#endif
irq_exit();
}
......
arch/x86_64/kernel/head64.c
View file @ 162b5250
......@@ -79,6 +79,9 @@ void __init x86_64_start_kernel(char * real_mode_data)
clear_bss();
pda_init(0);
copy_bootdata(real_mode_data);
/* default console: */
if (!strstr(saved_command_line, "console="))
strcat(saved_command_line, " console=tty0");
s = strstr(saved_command_line, "earlyprintk=");
if (s != NULL)
setup_early_printk(s+12);
......
arch/x86_64/kernel/io_apic.c
View file @ 162b5250
......@@ -1110,7 +1110,7 @@ static void __init setup_ioapic_ids_from_mpc (void)
*/
static int __init timer_irq_works(void)
{
unsigned int t1 = jiffies;
unsigned long t1 = jiffies;
local_irq_enable();
/* Let ten ticks pass... */
......@@ -1123,6 +1123,8 @@ static int __init timer_irq_works(void)
* might have cached one ExtINT interrupt. Finally, at
* least one tick may be lost due to delays.
*/
/* jiffies wrap? */
if (jiffies - t1 > 4)
return 1;
return 0;
......
arch/x86_64/kernel/process.c
View file @ 162b5250
This diff is collapsed.
arch/x86_64/kernel/ptrace.c
View file @ 162b5250
......@@ -26,6 +26,7 @@
#include <asm/ldt.h>
#include <asm/desc.h>
#include <asm/proto.h>
#include <asm/ia32.h>
/*
* does not yet catch signals sent when the child dies.
......@@ -322,6 +323,13 @@ asmlinkage long sys_ptrace(long request, long pid, long addr, long data)
wake_up_process(child);
ret = 0;
break;
}
#ifdef CONFIG_IA32_EMULATION
/* This makes only sense with 32bit programs. Allow a
64bit debugger to fully examine them too. Better
don't use it against 64bit processes, use
PTRACE_ARCH_PRCTL instead. */
case PTRACE_SET_THREAD_AREA: {
int old;
get_user(old, &((struct user_desc *)data)->entry_number);
......@@ -338,7 +346,13 @@ asmlinkage long sys_ptrace(long request, long pid, long addr, long data)
put_user(old, &((struct user_desc *)data)->entry_number);
break;
}
}
#endif
/* normal 64bit interface to access TLS data.
Works just like arch_prctl, except that the arguments
are reversed. */
case PTRACE_ARCH_PRCTL:
ret = do_arch_prctl(child, data, addr);
break;
/*
* make the child exit. Best I can do is send it a sigkill.
......
arch/x86_64/kernel/setup64.c
View file @ 162b5250
......@@ -22,6 +22,7 @@
#include <asm/i387.h>
#include <asm/percpu.h>
#include <asm/mtrr.h>
#include <asm/proto.h>
char x86_boot_params[2048] __initdata = {0,};
......@@ -29,9 +30,6 @@ unsigned long cpu_initialized __initdata = 0;
struct x8664_pda cpu_pda[NR_CPUS] __cacheline_aligned;
extern void system_call(void);
extern void ia32_cstar_target(void);
extern struct task_struct init_task;
extern unsigned char __per_cpu_start[], __per_cpu_end[];
......@@ -130,6 +128,24 @@ void pda_init(int cpu)
#define EXCEPTION_STK_ORDER 0 /* >= N_EXCEPTION_STACKS*EXCEPTION_STKSZ */
char boot_exception_stacks[N_EXCEPTION_STACKS*EXCEPTION_STKSZ];
void syscall_init(void)
{
/*
* LSTAR and STAR live in a bit strange symbiosis.
* They both write to the same internal register. STAR allows to set CS/DS
* but only a 32bit target. LSTAR sets the 64bit rip.
*/
wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
wrmsrl(MSR_LSTAR, system_call);
#ifdef CONFIG_IA32_EMULATION
wrmsrl(MSR_CSTAR, ia32_cstar_target);
#endif
/* Flags to clear on syscall */
wrmsrl(MSR_SYSCALL_MASK, EF_TF|EF_DF|EF_IE|0x3000);
}
/*
* cpu_init() initializes state that is per-CPU. Some data is already
* initialized (naturally) in the bootstrap process, such as the GDT
......@@ -188,20 +204,7 @@ void __init cpu_init (void)
asm volatile("pushfq ; popq %%rax ; btr $14,%%rax ; pushq %%rax ; popfq" ::: "eax");
/*
* LSTAR and STAR live in a bit strange symbiosis.
* They both write to the same internal register. STAR allows to set CS/DS
* but only a 32bit target. LSTAR sets the 64bit rip.
*/
wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
wrmsrl(MSR_LSTAR, system_call);
#ifdef CONFIG_IA32_EMULATION
wrmsrl(MSR_CSTAR, ia32_cstar_target);
#endif
/* Flags to clear on syscall */
wrmsrl(MSR_SYSCALL_MASK, EF_TF|EF_DF|EF_IE|0x3000);
syscall_init();
wrmsrl(MSR_FS_BASE, 0);
wrmsrl(MSR_KERNEL_GS_BASE, 0);
......
arch/x86_64/kernel/signal.c
View file @ 162b5250
......@@ -96,14 +96,6 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc, unsigned long *p
#define COPY(x) err |= __get_user(regs->x, &sc->x)
{
unsigned int seg;
err |= __get_user(seg, &sc->gs);
load_gs_index(seg);
err |= __get_user(seg, &sc->fs);
loadsegment(fs,seg);
}
COPY(rdi); COPY(rsi); COPY(rbp); COPY(rsp); COPY(rbx);
COPY(rdx); COPY(rcx); COPY(rip);
COPY(r8);
......@@ -189,13 +181,10 @@ asmlinkage long sys_rt_sigreturn(struct pt_regs regs)
static inline int
setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs, unsigned long mask, struct task_struct *me)
{
int tmp, err = 0;
int err = 0;
tmp = 0;
__asm__("movl %%gs,%0" : "=r"(tmp): "0"(tmp));
err |= __put_user(tmp, (unsigned int *)&sc->gs);
__asm__("movl %%fs,%0" : "=r"(tmp): "0"(tmp));
err |= __put_user(tmp, (unsigned int *)&sc->fs);
err |= __put_user(0, &sc->gs);
err |= __put_user(0, &sc->fs);
err |= __put_user(regs->rdi, &sc->rdi);
err |= __put_user(regs->rsi, &sc->rsi);
......
arch/x86_64/kernel/suspend.c
View file @ 162b5250
......@@ -26,6 +26,7 @@
#include <asm/acpi.h>
#include <asm/tlbflush.h>
#include <asm/io.h>
#include <asm/proto.h>
static struct saved_context saved_context;
......@@ -58,10 +59,9 @@ void save_processor_state (void)
asm volatile ("movw %%gs, %0" : "=m" (saved_context.gs));
asm volatile ("movw %%ss, %0" : "=m" (saved_context.ss));
asm volatile ("swapgs");
rdmsrl(0xc0000100, saved_context.fs_base);
rdmsrl(0xc0000101, saved_context.gs_base);
asm volatile ("swapgs");
rdmsrl(MSR_FS_BASE, saved_context.fs_base);
rdmsrl(MSR_GS_BASE, saved_context.gs_base);
rdmsrl(MSR_KERNEL_GS_BASE, saved_context.gs_kernel_base);
/*
* control registers
......@@ -99,10 +99,9 @@ void restore_processor_state(void)
load_gs_index(saved_context.gs);
asm volatile ("movw %0, %%ss" :: "r" (saved_context.ss));
asm volatile ("swapgs");
wrmsrl(0xc0000100, saved_context.fs_base);
wrmsrl(0xc0000101, saved_context.gs_base);
asm volatile ("swapgs");
wrmsrl(MSR_FS_BASE, saved_context.fs_base);
wrmsrl(MSR_GS_BASE, saved_context.gs_base);
wrmsrl(MSR_KERNEL_GS_BASE, saved_context.gs_kernel_base);
/*
* now restore the descriptor tables to their proper values
......
arch/x86_64/kernel/time.c
View file @ 162b5250
......@@ -30,7 +30,7 @@
#include <asm/apic.h>
#endif
u64 jiffies_64;
u64 jiffies_64 = INITIAL_JIFFIES;
extern int using_apic_timer;
......@@ -47,8 +47,8 @@ int hpet_report_lost_ticks; /* command line option */
struct hpet_data __hpet __section_hpet; /* address, quotient, trigger, hz */
volatile unsigned long __jiffies __section_jiffies;
unsigned long __wall_jiffies __section_wall_jiffies;
volatile unsigned long __jiffies __section_jiffies = INITIAL_JIFFIES;
unsigned long __wall_jiffies __section_wall_jiffies = INITIAL_JIFFIES;
struct timespec __xtime __section_xtime;
struct timezone __sys_tz __section_sys_tz;
......
arch/x86_64/lib/getuser.S
View file @ 162b5250
......@@ -30,7 +30,7 @@
#include <asm/thread_info.h>
.text
.p2align
.p2align 4
.globl __get_user_1
__get_user_1:
GET_THREAD_INFO(%rbx)
......@@ -40,7 +40,7 @@ __get_user_1:
xorq %rax,%rax
ret
.p2align
.p2align 4
.globl __get_user_2
__get_user_2:
GET_THREAD_INFO(%rbx)
......@@ -52,7 +52,7 @@ __get_user_2:
xorq %rax,%rax
ret
.p2align
.p2align 4
.globl __get_user_4
__get_user_4:
GET_THREAD_INFO(%rbx)
......@@ -64,7 +64,7 @@ __get_user_4:
xorq %rax,%rax
ret
.p2align
.p2align 4
.globl __get_user_8
__get_user_8:
GET_THREAD_INFO(%rbx)
......
arch/x86_64/mm/pageattr.c
View file @ 162b5250
......@@ -53,7 +53,7 @@ static struct page *split_large_page(unsigned long address, pgprot_t prot)
static void flush_kernel_map(void *address)
{
if (address && cpu_has_clflush) {
if (0 && address && cpu_has_clflush) {
/* is this worth it? */
int i;
for (i = 0; i < PAGE_SIZE; i += boot_cpu_data.x86_clflush_size)
......
arch/x86_64/pci/direct.c
View file @ 162b5250
......@@ -196,21 +196,35 @@ static struct pci_ops pci_direct_conf2 = {
static int __devinit pci_sanity_check(struct pci_ops *o)
{
u32 x = 0;
struct pci_bus bus; /* Fake bus and device */
struct pci_dev dev;
int retval = 0;
struct pci_bus *bus; /* Fake bus and device */
struct pci_dev *dev;
if (pci_probe & PCI_NO_CHECKS)
return 1;
bus.number = 0;
dev.bus = &bus;
for(dev.devfn=0; dev.devfn < 0x100; dev.devfn++)
if ((!o->read(&bus, dev.devfn, PCI_CLASS_DEVICE, 2, &x) &&
bus = kmalloc(sizeof(*bus), GFP_ATOMIC);
dev = kmalloc(sizeof(*dev), GFP_ATOMIC);
if (!bus || !dev) {
printk(KERN_ERR "Out of memory in %s\n", __FUNCTION__);
goto exit;
}
bus->number = 0;
dev->bus = bus;
for(dev->devfn=0; dev->devfn < 0x100; dev->devfn++)
if ((!o->read(bus, dev->devfn, PCI_CLASS_DEVICE, 2, &x) &&
(x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)) ||
(!o->read(&bus, dev.devfn, PCI_VENDOR_ID, 2, &x) &&
(x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)))
return 1;
(!o->read(bus, dev->devfn, PCI_VENDOR_ID, 2, &x) &&
(x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ))) {
retval = 1;
goto exit;
}
DBG("PCI: Sanity check failed\n");
return 0;
exit:
kfree(dev);
kfree(bus);
return retval;
}
static int __init pci_direct_init(void)
......@@ -218,7 +232,7 @@ static int __init pci_direct_init(void)
unsigned int tmp;
unsigned long flags;
local_save_flags(flags); local_irq_disable();
local_irq_save(flags);
/*
* Check if configuration type 1 works.
......@@ -261,7 +275,6 @@ static int __init pci_direct_init(void)
}
local_irq_restore(flags);
pci_root_ops = NULL;
return 0;
}
......
arch/x86_64/pci/irq.c
View file @ 162b5250
......@@ -109,7 +109,7 @@ static void __init pirq_peer_trick(void)
*/
if (busmap[i] && pci_scan_bus(i, pci_root_bus->ops, NULL))
printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
pcibios_last_bus = -1;
//pcibios_last_bus = -1;
}
/*
......@@ -291,14 +291,14 @@ static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq
{
irq = read_config_nybble(router, 0x56, pirq - 1);
}
printk(KERN_INFO "AMD: dev %04x:%04x, router pirq : %d get irq : %2d\n",
printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
dev->vendor, dev->device, pirq, irq);
return irq;
}
static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
{
printk(KERN_INFO "AMD: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
dev->vendor, dev->device, pirq, irq);
if (pirq <= 4)
{
......
arch/x86_64/pci/legacy.c
View file @ 162b5250
/*
* legacy.c - traditional, old school PCI bus probing
*/
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/pci.h>
#include "pci.h"
/*
......@@ -12,28 +12,39 @@
void __devinit pcibios_fixup_peer_bridges(void)
{
int n;
struct pci_bus bus;
struct pci_dev dev;
struct pci_bus *bus;
struct pci_dev *dev;
u16 l;
if (pcibios_last_bus <= 0 || pcibios_last_bus > 0xff)
if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff)
return;
DBG("PCI: Peer bridge fixup\n");
bus = kmalloc(sizeof(*bus), GFP_ATOMIC);
dev = kmalloc(sizeof(*dev), GFP_ATOMIC);
if (!bus || !dev) {
printk(KERN_ERR "Out of memory in %s\n", __FUNCTION__);
goto exit;
}
for (n=0; n <= pcibios_last_bus; n++) {
if (pci_bus_exists(&pci_root_buses, n))
continue;
bus.number = n;
bus.ops = pci_root_ops;
dev.bus = &bus;
for(dev.devfn=0; dev.devfn<256; dev.devfn += 8)
if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
bus->number = n;
bus->ops = pci_root_ops;
dev->bus = bus;
for (dev->devfn=0; dev->devfn<256; dev->devfn += 8)
if (!pci_read_config_word(dev, PCI_VENDOR_ID, &l) &&
l != 0x0000 && l != 0xffff) {
DBG("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l);
DBG("Found device at %02x:%02x [%04x]\n", n, dev->devfn, l);
printk(KERN_INFO "PCI: Discovered peer bus %02x\n", n);
pci_scan_bus(n, pci_root_ops, NULL);
break;
}
}
exit:
kfree(dev);
kfree(bus);
}
static int __init pci_legacy_init(void)
......
arch/x86_64/pci/pci.h
View file @ 162b5250
......@@ -67,7 +67,6 @@ extern unsigned int pcibios_irq_mask;
extern int pcibios_scanned;
extern spinlock_t pci_config_lock;
void pcibios_fixup_irqs(void);
int pirq_enable_irq(struct pci_dev *dev);
extern int (*pcibios_enable_irq)(struct pci_dev *dev);
......
drivers/Makefile
View file @ 162b5250
......@@ -11,9 +11,13 @@ obj-$(CONFIG_ACPI) += acpi/
# PnP must come after ACPI since it will eventually need to check if acpi
# was used and do nothing if so
obj-$(CONFIG_PNP) += pnp/
# char/ comes before serial/ etc so that the VT console is the boot-time
# default.
obj-y += char/
obj-y += serial/
obj-$(CONFIG_PARPORT) += parport/
obj-y += base/ char/ block/ misc/ net/ media/
obj-y += base/ block/ misc/ net/ media/
obj-$(CONFIG_NUBUS) += nubus/
obj-$(CONFIG_ATM) += atm/
obj-$(CONFIG_IDE) += ide/
......
drivers/block/genhd.c
View file @ 162b5250
......@@ -91,9 +91,6 @@ int register_blkdev(unsigned int major, const char *name)
struct blk_major_name **n, *p;
int index, ret = 0;
if (devfs_only())
return 0;
/* temporary */
if (major == 0) {
down_read(&block_subsys.rwsem);
......@@ -141,13 +138,9 @@ int register_blkdev(unsigned int major, const char *name)
int unregister_blkdev(unsigned int major, const char *name)
{
struct blk_major_name **n, *p;
int index;
int index = major_to_index(major);
int ret = 0;
if (devfs_only())
return 0;
index = major_to_index(major);
down_write(&block_subsys.rwsem);
for (n = &major_names[index]; *n; n = &(*n)->next)
if ((*n)->major == major)
......
drivers/eisa/eisa-bus.c
View file @ 162b5250
......@@ -83,8 +83,10 @@ static int eisa_bus_match (struct device *dev, struct device_driver *drv)
return 0;
while (strlen (eids->sig)) {
if (!strcmp (eids->sig, edev->id.sig))
if (!strcmp (eids->sig, edev->id.sig)) {
edev->id.driver_data = eids->driver_data;
return 1;
}
eids++;
}
......
drivers/eisa/virtual_root.c
View file @ 162b5250
......@@ -13,14 +13,19 @@
#include <linux/module.h>
#include <linux/init.h>
/* The default EISA device parent (virtual root device). */
static struct device eisa_root_dev = {
.name = "Virtual EISA Bridge",
.bus_id = "eisa",
/* The default EISA device parent (virtual root device).
* Now use a platform device, since that's the obvious choice. */
static struct platform_device eisa_root_dev = {
.name = "eisa",
.id = 0,
.dev = {
.name = "Virtual EISA Bridge",
},
};
static struct eisa_root_device eisa_bus_root = {
.dev = &eisa_root_dev,
.dev = &eisa_root_dev.dev,
.bus_base_addr = 0,
.res = &ioport_resource,
.slots = EISA_MAX_SLOTS,
......@@ -30,16 +35,16 @@ static int virtual_eisa_root_init (void)
{
int r;
if ((r = device_register (&eisa_root_dev))) {
if ((r = platform_device_register (&eisa_root_dev))) {
return r;
}
eisa_root_dev.driver_data = &eisa_bus_root;
eisa_root_dev.dev.driver_data = &eisa_bus_root;
if (eisa_root_register (&eisa_bus_root)) {
/* A real bridge may have been registered before
* us. So quietly unregister. */
device_unregister (&eisa_root_dev);
platform_device_unregister (&eisa_root_dev);
return -1;
}
......
drivers/i2c/i2c-algo-bit.c
View file @ 162b5250
This diff is collapsed.
drivers/i2c/i2c-algo-ibm_ocp.c
View file @ 162b5250
......@@ -55,20 +55,12 @@
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/version.h>
#include <linux/init.h>
#include <asm/uaccess.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/i2c.h>
#include "i2c-algo-ibm_ocp.h"
//ACC#include <asm/ocp.h>
#ifdef MODULE_LICENSE
MODULE_LICENSE("GPL");
#endif
#include <linux/i2c-algo-ibm_ocp.h>
#include <asm/ocp.h>
/* ----- global defines ----------------------------------------------- */
......@@ -79,26 +71,13 @@ MODULE_LICENSE("GPL");
/* debug the protocol by showing transferred bits */
#define DEF_TIMEOUT 5
/* debugging - slow down transfer to have a look at the data .. */
/* I use this with two leds&resistors, each one connected to sda,scl */
/* respectively. This makes sure that the algorithm works. Some chips */
/* might not like this, as they have an internal timeout of some mils */
/*
#define SLO_IO jif=jiffies;while(time_before_eq(jiffies,jif+i2c_table[minor].veryslow))\
if (need_resched) schedule();
*/
/* ----- global variables --------------------------------------------- */
#ifdef SLO_IO
int jif;
#endif
/* module parameters:
*/
static int i2c_debug=0;
static int iic_scan=0; /* have a look at what's hanging 'round */
/* --- setting states on the bus with the right timing: --------------- */
......@@ -758,7 +737,7 @@ static int iic_xfer(struct i2c_adapter *i2c_adap,
// Check to see if the bus is busy
//
ret = iic_inb(adap, iic->extsts);
// Mask off the irrelevant bits
// Mask off the irrelevent bits
ret = ret & 0x70;
// When the bus is free, the BCS bits in the EXTSTS register are 0b100
if(ret != 0x40) return IIC_ERR_LOST_ARB;
......@@ -858,17 +837,13 @@ static u32 iic_func(struct i2c_adapter *adap)
/* -----exported algorithm data: ------------------------------------- */
static struct i2c_algorithm iic_algo = {
"IBM on-chip IIC algorithm",
I2C_ALGO_OCP,
iic_xfer,
NULL,
NULL, /* slave_xmit */
NULL, /* slave_recv */
algo_control, /* ioctl */
iic_func, /* functionality */
.name = "IBM on-chip IIC algorithm",
.id = I2C_ALGO_OCP,
.master_xfer = iic_xfer,
.algo_control = algo_control,
.functionality = iic_func,
};
/*
* registering functions to load algorithms at runtime
*/
......@@ -892,19 +867,8 @@ int i2c_ocp_add_bus(struct i2c_adapter *adap)
adap->timeout = 100; /* default values, should */
adap->retries = 3; /* be replaced by defines */
#ifdef MODULE
MOD_INC_USE_COUNT;
#endif
iic_init(iic_adap);
i2c_add_adapter(adap);
/* scan bus */
/* By default scanning the bus is turned off. */
if (iic_scan) {
printk(KERN_INFO " i2c-algo-iic.o: scanning bus %s.\n",
adap->name);
}
return 0;
}
......@@ -914,31 +878,7 @@ int i2c_ocp_add_bus(struct i2c_adapter *adap)
//
int i2c_ocp_del_bus(struct i2c_adapter *adap)
{
int res;
if ((res = i2c_del_adapter(adap)) < 0)
return res;
DEB2(printk(KERN_DEBUG "i2c-algo-iic.o: adapter unregistered: %s\n",adap->name));
#ifdef MODULE
MOD_DEC_USE_COUNT;
#endif
return 0;
}
//
// Done
//
int __init i2c_algo_iic_init (void)
{
printk(KERN_INFO "IBM On-chip iic (i2c) algorithm module 2002.27.03\n");
return 0;
}
void i2c_algo_iic_exit(void)
{
return;
return i2c_del_adapter(adap);
}
......@@ -951,16 +891,10 @@ EXPORT_SYMBOL(i2c_ocp_del_bus);
//
MODULE_AUTHOR("MontaVista Software <www.mvista.com>");
MODULE_DESCRIPTION("PPC 405 iic algorithm");
MODULE_LICENSE("GPL");
MODULE_PARM(iic_test, "i");
MODULE_PARM(iic_scan, "i");
MODULE_PARM(i2c_debug,"i");
MODULE_PARM_DESC(iic_test, "Test if the I2C bus is available");
MODULE_PARM_DESC(iic_scan, "Scan for active chips on the bus");
MODULE_PARM_DESC(i2c_debug,
"debug level - 0 off; 1 normal; 2,3 more verbose; 9 iic-protocol");
module_init(i2c_algo_iic_init);
module_exit(i2c_algo_iic_exit);
drivers/i2c/i2c-algo-pcf.c
View file @ 162b5250
......@@ -49,7 +49,6 @@
/* module parameters:
*/
static int i2c_debug=0;
static int pcf_scan=0; /* have a look at what's hanging 'round */
/* --- setting states on the bus with the right timing: --------------- */
......@@ -423,12 +422,6 @@ static int pcf_xfer(struct i2c_adapter *i2c_adap,
return (i);
}
static int algo_control(struct i2c_adapter *adapter,
unsigned int cmd, unsigned long arg)
{
return 0;
}
static u32 pcf_func(struct i2c_adapter *adap)
{
return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
......@@ -438,14 +431,10 @@ static u32 pcf_func(struct i2c_adapter *adap)
/* -----exported algorithm data: ------------------------------------- */
static struct i2c_algorithm pcf_algo = {
"PCF8584 algorithm",
I2C_ALGO_PCF,
pcf_xfer,
NULL,
NULL, /* slave_xmit */
NULL, /* slave_recv */
algo_control, /* ioctl */
pcf_func, /* functionality */
.name = "PCF8584 algorithm",
.id = I2C_ALGO_PCF,
.master_xfer = pcf_xfer,
.functionality = pcf_func,
};
/*
......@@ -453,8 +442,8 @@ static struct i2c_algorithm pcf_algo = {
*/
int i2c_pcf_add_bus(struct i2c_adapter *adap)
{
int i, status;
struct i2c_algo_pcf_data *pcf_adap = adap->algo_data;
int rval;
DEB2(printk(KERN_DEBUG "i2c-algo-pcf.o: hw routines for %s registered.\n",
adap->name));
......@@ -467,36 +456,10 @@ int i2c_pcf_add_bus(struct i2c_adapter *adap)
adap->timeout = 100; /* default values, should */
adap->retries = 3; /* be replaced by defines */
if ((i = pcf_init_8584(pcf_adap))) {
return i;
}
i2c_add_adapter(adap);
/* scan bus */
if (pcf_scan) {
printk(KERN_INFO " i2c-algo-pcf.o: scanning bus %s.\n",
adap->name);
for (i = 0x00; i < 0xff; i+=2) {
if (wait_for_bb(pcf_adap)) {
printk(KERN_INFO " i2c-algo-pcf.o: scanning bus %s - TIMEOUTed.\n",
adap->name);
break;
}
i2c_outb(pcf_adap, i);
i2c_start(pcf_adap);
if ((wait_for_pin(pcf_adap, &status) >= 0) &&
((status & I2C_PCF_LRB) == 0)) {
printk("(%02x)",i>>1);
} else {
printk(".");
}
i2c_stop(pcf_adap);
udelay(pcf_adap->udelay);
}
printk("\n");
}
return 0;
rval = pcf_init_8584(pcf_adap);
if (!rval)
i2c_add_adapter(adap);
return rval;
}
......@@ -512,9 +475,6 @@ MODULE_AUTHOR("Hans Berglund <hb@spacetec.no>");
MODULE_DESCRIPTION("I2C-Bus PCF8584 algorithm");
MODULE_LICENSE("GPL");
MODULE_PARM(pcf_scan, "i");
MODULE_PARM(i2c_debug,"i");
MODULE_PARM_DESC(pcf_scan, "Scan for active chips on the bus");
MODULE_PARM_DESC(i2c_debug,
"debug level - 0 off; 1 normal; 2,3 more verbose; 9 pcf-protocol");
drivers/i2c/i2c-core.c
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drivers/pnp/Kconfig
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......@@ -30,15 +30,6 @@ config PNP_NAMES
If unsure, say Y.
config PNP_CARD
bool "Plug and Play card services"
depends on PNP
help
Select Y if you want the PnP Layer to manage cards. Cards are groups
of PnP devices. Some drivers, especially PnP sound card drivers, use
these cards. If you want to use the protocol ISAPNP you will need to
say Y here.
config PNP_DEBUG
bool "PnP Debug Messages"
depends on PNP
......@@ -51,7 +42,7 @@ comment "Protocols"
config ISAPNP
bool "ISA Plug and Play support (EXPERIMENTAL)"
depends on PNP && EXPERIMENTAL && PNP_CARD
depends on PNP && EXPERIMENTAL
help
Say Y here if you would like support for ISA Plug and Play devices.
Some information is in <file:Documentation/isapnp.txt>.
......
drivers/pnp/Makefile
View file @ 162b5250
......@@ -2,9 +2,7 @@
# Makefile for the Linux Plug-and-Play Support.
#
pnp-card-$(CONFIG_PNP_CARD) = card.o
obj-y := core.o driver.o resource.o manager.o support.o interface.o quirks.o names.o system.o $(pnp-card-y)
obj-y := core.o card.o driver.o resource.o manager.o support.o interface.o quirks.o names.o system.o
obj-$(CONFIG_PNPBIOS) += pnpbios/
obj-$(CONFIG_ISAPNP) += isapnp/
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