ACPI: HMAT: Introduce 2 levels of generic port access class
In order to compute access0 and access1 classes for CXL memory, 2 levels of generic port information must be stored. Access0 will indicate the generic port access coordinates to the closest initiator and access1 will indicate the generic port access coordinates to the cloest CPU. Cc: Rafael J. Wysocki <rafael@kernel.org> Reviewed-by:Jonathan Cameron <Jonathan.Cameron@huawei.com> Tested-by:
Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by:
Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20240308220055.2172956-4-dave.jiang@intel.comSigned-off-by:
Dan Williams <dan.j.williams@intel.com>
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