Commit 176f26bc authored by Lokesh Vutla's avatar Lokesh Vutla Committed by Tony Lindgren

ARM: dts: Add support for dra762 abz package

dra762 abz package is pin compatible with dra742 and few peripherals
like DDR with upgraded speed. Add dt support for this SoC.
Reported-by: default avatarPraneeth Bajjuri <praneeth@ti.com>
Tested-by: default avatarPraneeth Bajjuri <praneeth@ti.com>
Signed-off-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
[khilman: forward port from ti-linux-5.4.y]
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent cb31bbfa
......@@ -3,7 +3,7 @@
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "dra76x.dtsi"
#include "dra74x-p.dtsi"
#include "am57-pruss.dtsi"
/ {
......@@ -25,10 +25,6 @@ &usb3_tm {
status = "disabled";
};
&usb4_tm {
status = "disabled";
};
&atl_tm {
status = "disabled";
};
......@@ -36,10 +36,6 @@ &mmc2 {
pinctrl-2 = <&mmc2_pins_default>;
};
&m_can0 {
status = "disabled";
};
&emif1 {
status = "okay";
};
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "dra74x.dtsi"
/ {
compatible = "ti,dra762", "ti,dra7";
ocp {
emif1: emif@4c000000 {
compatible = "ti,emif-dra7xx";
reg = <0x4c000000 0x200>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
};
/* MCAN interrupts are hard-wired to irqs 67, 68 */
&crossbar_mpu {
ti,irqs-skip = <10 67 68 133 139 140>;
};
......@@ -9,13 +9,6 @@ / {
compatible = "ti,dra762", "ti,dra7";
ocp {
emif1: emif@4c000000 {
compatible = "ti,emif-dra7xx";
reg = <0x4c000000 0x200>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
target-module@42c01900 {
compatible = "ti,sysc-dra7-mcan", "ti,sysc";
ranges = <0x0 0x42c00000 0x2000>;
......@@ -90,11 +83,6 @@ csi2_1: port@1 {
};
};
/* MCAN interrupts are hard-wired to irqs 67, 68 */
&crossbar_mpu {
ti,irqs-skip = <10 67 68 133 139 140>;
};
&scm_conf_clocks {
dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc {
#clock-cells = <0>;
......
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