Commit 18022894 authored by James Hogan's avatar James Hogan Committed by Ralf Baechle

MIPS: traps: 64bit kernels should read CP0_EBase 64bit

When reading the CP0_EBase register containing the WG (write gate) bit,
the ebase variable should be set to the full value of the register, i.e.
on a 64-bit kernel the full 64-bit width of the register via
read_cp0_ebase_64(), and on a 32-bit kernel the full 32-bit width
including bits 31:30 which may be writeable.
Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Signed-off-by: default avatarMatt Redfearn <matt.redfearn@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14148/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 72bc8c75
...@@ -2215,8 +2215,17 @@ void __init trap_init(void) ...@@ -2215,8 +2215,17 @@ void __init trap_init(void)
} else { } else {
ebase = CAC_BASE; ebase = CAC_BASE;
if (cpu_has_mips_r2_r6) if (cpu_has_mips_r2_r6) {
ebase += (read_c0_ebase() & 0x3ffff000); if (cpu_has_ebase_wg) {
#ifdef CONFIG_64BIT
ebase = (read_c0_ebase_64() & ~0xfff);
#else
ebase = (read_c0_ebase() & ~0xfff);
#endif
} else {
ebase += (read_c0_ebase() & 0x3ffff000);
}
}
} }
if (cpu_has_mmips) { if (cpu_has_mmips) {
......
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