Commit 18271fa4 authored by Jeff Garzik's avatar Jeff Garzik

Merge Intel EtherExpress PRO/100 net driver "e100" from Intel,

version 2.0.19, plus boolean cleanups.
Bump version to 2.0.20-pre1.

Contributors: Eli Kupermann @ Intel, Amir Noam @ Intel
parent 2d8a9d3f
...@@ -166,7 +166,8 @@ if [ "$CONFIG_NET_ETHERNET" = "y" ]; then ...@@ -166,7 +166,8 @@ if [ "$CONFIG_NET_ETHERNET" = "y" ]; then
tristate ' Digi Intl. RightSwitch SE-X support' CONFIG_DGRS tristate ' Digi Intl. RightSwitch SE-X support' CONFIG_DGRS
fi fi
dep_tristate ' Davicom DM910x/DM980x support' CONFIG_DM9102 $CONFIG_PCI dep_tristate ' Davicom DM910x/DM980x support' CONFIG_DM9102 $CONFIG_PCI
dep_tristate ' EtherExpressPro/100 support' CONFIG_EEPRO100 $CONFIG_PCI dep_tristate ' EtherExpressPro/100 support (eepro100, original Becker driver)' CONFIG_EEPRO100 $CONFIG_PCI
dep_tristate ' EtherExpressPro/100 support (e100, Alternate Intel driver)' CONFIG_E100 $CONFIG_PCI
dep_tristate ' Mylex EISA LNE390A/B support (EXPERIMENTAL)' CONFIG_LNE390 $CONFIG_EISA $CONFIG_EXPERIMENTAL dep_tristate ' Mylex EISA LNE390A/B support (EXPERIMENTAL)' CONFIG_LNE390 $CONFIG_EISA $CONFIG_EXPERIMENTAL
dep_tristate ' Myson MTD-8xx PCI Ethernet support' CONFIG_FEALNX $CONFIG_PCI dep_tristate ' Myson MTD-8xx PCI Ethernet support' CONFIG_FEALNX $CONFIG_PCI
dep_tristate ' National Semiconductor DP8381x series PCI Ethernet support' CONFIG_NATSEMI $CONFIG_PCI dep_tristate ' National Semiconductor DP8381x series PCI Ethernet support' CONFIG_NATSEMI $CONFIG_PCI
......
...@@ -25,6 +25,9 @@ ifeq ($(CONFIG_TULIP),y) ...@@ -25,6 +25,9 @@ ifeq ($(CONFIG_TULIP),y)
obj-y += tulip/tulip.o obj-y += tulip/tulip.o
endif endif
ifeq ($(CONFIG_E100),y)
obj-y += e1000/e100.o
endif
ifeq ($(CONFIG_E1000),y) ifeq ($(CONFIG_E1000),y)
obj-y += e1000/e1000.o obj-y += e1000/e1000.o
endif endif
...@@ -36,6 +39,7 @@ endif ...@@ -36,6 +39,7 @@ endif
subdir-$(CONFIG_NET_PCMCIA) += pcmcia subdir-$(CONFIG_NET_PCMCIA) += pcmcia
subdir-$(CONFIG_NET_WIRELESS) += wireless subdir-$(CONFIG_NET_WIRELESS) += wireless
subdir-$(CONFIG_TULIP) += tulip subdir-$(CONFIG_TULIP) += tulip
subdir-$(CONFIG_E100) += e100
subdir-$(CONFIG_E1000) += e1000 subdir-$(CONFIG_E1000) += e1000
subdir-$(CONFIG_IRDA) += irda subdir-$(CONFIG_IRDA) += irda
subdir-$(CONFIG_TR) += tokenring subdir-$(CONFIG_TR) += tokenring
......
#
# Makefile for the Intel's E100 ethernet driver
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
# Note 2! The CFLAGS definitions are now in the main makefile...
O_TARGET := e100.o
obj-y := e100_main.o e100_config.o e100_proc.o e100_phy.o \
e100_eeprom.o
obj-m := $(O_TARGET)
include $(TOPDIR)/Rules.make
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/*******************************************************************************
This software program is available to you under a choice of one of two
licenses. You may choose to be licensed under either the GNU General Public
License (GPL) Version 2, June 1991, available at
http://www.fsf.org/copyleft/gpl.html, or the Intel BSD + Patent License, the
text of which follows:
Recipient has requested a license and Intel Corporation ("Intel") is willing
to grant a license for the software entitled Linux Base Driver for the
Intel(R) PRO/100 Family of Adapters (e100) (the "Software") being provided
by Intel Corporation. The following definitions apply to this license:
"Licensed Patents" means patent claims licensable by Intel Corporation which
are necessarily infringed by the use of sale of the Software alone or when
combined with the operating system referred to below.
"Recipient" means the party to whom Intel delivers this Software.
"Licensee" means Recipient and those third parties that receive a license to
any operating system available under the GNU Public License version 2.0 or
later.
Copyright (c) 1999 - 2002 Intel Corporation.
All rights reserved.
The license is provided to Recipient and Recipient's Licensees under the
following terms.
Redistribution and use in source and binary forms of the Software, with or
without modification, are permitted provided that the following conditions
are met:
Redistributions of source code of the Software may retain the above
copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form of the Software may reproduce the above
copyright notice, this list of conditions and the following disclaimer in
the documentation and/or materials provided with the distribution.
Neither the name of Intel Corporation nor the names of its contributors
shall be used to endorse or promote products derived from this Software
without specific prior written permission.
Intel hereby grants Recipient and Licensees a non-exclusive, worldwide,
royalty-free patent license under Licensed Patents to make, use, sell, offer
to sell, import and otherwise transfer the Software, if any, in source code
and object code form. This license shall include changes to the Software
that are error corrections or other minor changes to the Software that do
not add functionality or features when the Software is incorporated in any
version of an operating system that has been distributed under the GNU
General Public License 2.0 or later. This patent license shall apply to the
combination of the Software and any operating system licensed under the GNU
Public License version 2.0 or later if, at the time Intel provides the
Software to Recipient, such addition of the Software to the then publicly
available versions of such operating systems available under the GNU Public
License version 2.0 or later (whether in gold, beta or alpha form) causes
such combination to be covered by the Licensed Patents. The patent license
shall not apply to any other combinations which include the Software. NO
hardware per se is licensed hereunder.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR IT CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
ANY LOSS OF USE; DATA, OR PROFITS; OR BUSINESS INTERUPTION) HOWEVER CAUSED
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR
TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef _E100_CONFIG_INC_
#define _E100_CONFIG_INC_
#include "e100.h"
#define E100_CONFIG(bdp, X) ((bdp)->config[0] = max_t(u8, (bdp)->config[0], (X)+1))
#define CB_CFIG_MIN_PARAMS 8
/* byte 0 bit definitions*/
#define CB_CFIG_BYTE_COUNT_MASK BIT_0_5 /* Byte count occupies bit 5-0 */
/* byte 1 bit definitions*/
#define CB_CFIG_RXFIFO_LIMIT_MASK BIT_0_4 /* RxFifo limit mask */
#define CB_CFIG_TXFIFO_LIMIT_MASK BIT_4_7 /* TxFifo limit mask */
/* byte 2 bit definitions -- ADAPTIVE_IFS*/
/* word 3 bit definitions -- RESERVED*/
/* Changed for 82558 enhancements */
/* byte 3 bit definitions */
#define CB_CFIG_MWI_EN BIT_0 /* Enable MWI on PCI bus */
#define CB_CFIG_TYPE_EN BIT_1 /* Type Enable */
#define CB_CFIG_READAL_EN BIT_2 /* Enable Read Align */
#define CB_CFIG_TERMCL_EN BIT_3 /* Cache line write */
/* byte 4 bit definitions*/
#define CB_CFIG_RX_MIN_DMA_MASK BIT_0_6 /* Rx minimum DMA count mask */
/* byte 5 bit definitions*/
#define CB_CFIG_TX_MIN_DMA_MASK BIT_0_6 /* Tx minimum DMA count mask */
#define CB_CFIG_DMBC_EN BIT_7 /* Enable Tx/Rx min. DMA counts */
/* Changed for 82558 enhancements */
/* byte 6 bit definitions*/
#define CB_CFIG_LATE_SCB BIT_0 /* Update SCB After New Tx Start */
#define CB_CFIG_DIRECT_DMA_DIS BIT_1 /* Direct DMA mode */
#define CB_CFIG_TNO_INT BIT_2 /* Tx Not OK Interrupt */
#define CB_CFIG_TCO_STAT BIT_2 /* TCO statistics in 559 and above */
#define CB_CFIG_CI_INT BIT_3 /* Command Complete Interrupt */
#define CB_CFIG_EXT_TCB_DIS BIT_4 /* Extended TCB */
#define CB_CFIG_EXT_STAT_DIS BIT_5 /* Extended Stats */
#define CB_CFIG_SAVE_BAD_FRAMES BIT_7 /* Save Bad Frames Enabled */
/* byte 7 bit definitions*/
#define CB_CFIG_DISC_SHORT_FRAMES BIT_0 /* Discard Short Frames */
#define CB_CFIG_DYNTBD_EN BIT_7 /* Enable dynamic TBD */
/* Enable extended RFD's on D102 */
#define CB_CFIG_EXTENDED_RFD BIT_5
/* byte 8 bit definitions*/
#define CB_CFIG_503_MII BIT_0 /* 503 vs. MII mode */
/* byte 9 bit definitions -- pre-defined all zeros*/
#define CB_LINK_STATUS_WOL BIT_5
/* byte 10 bit definitions*/
#define CB_CFIG_NO_SRCADR BIT_3 /* No Source Address Insertion */
#define CB_CFIG_PREAMBLE_LEN BIT_4_5 /* Preamble Length */
#define CB_CFIG_LOOPBACK_MODE BIT_6_7 /* Loopback Mode */
#define CB_CFIG_LOOPBACK_NORMAL 0
#define CB_CFIG_LOOPBACK_INTERNAL BIT_6
#define CB_CFIG_LOOPBACK_EXTERNAL BIT_6_7
/* byte 11 bit definitions*/
#define CB_CFIG_LINEAR_PRIORITY BIT_0_2 /* Linear Priority */
/* byte 12 bit definitions*/
#define CB_CFIG_LINEAR_PRI_MODE BIT_0 /* Linear Priority mode */
#define CB_CFIG_IFS_MASK BIT_4_7 /* Interframe Spacing mask */
/* byte 13 bit definitions -- pre-defined all zeros*/
/* byte 14 bit definitions -- pre-defined 0xf2*/
/* byte 15 bit definitions*/
#define CB_CFIG_PROMISCUOUS BIT_0 /* Promiscuous Mode Enable */
#define CB_CFIG_BROADCAST_DIS BIT_1 /* Broadcast Mode Disable */
#define CB_CFIG_CRS_OR_CDT BIT_7 /* CRS Or CDT */
/* byte 16 bit definitions -- pre-defined all zeros*/
#define DFLT_FC_DELAY_LSB 0x1f /* Delay for outgoing Pause frames */
#define DFLT_NO_FC_DELAY_LSB 0x00 /* no flow control default value */
/* byte 17 bit definitions -- pre-defined 0x40*/
#define DFLT_FC_DELAY_MSB 0x01 /* Delay for outgoing Pause frames */
#define DFLT_NO_FC_DELAY_MSB 0x40 /* no flow control default value */
/* byte 18 bit definitions*/
#define CB_CFIG_STRIPPING BIT_0 /* Padding Disabled */
#define CB_CFIG_PADDING BIT_1 /* Padding Disabled */
#define CB_CFIG_CRC_IN_MEM BIT_2 /* Transfer CRC To Memory */
/* byte 19 bit definitions*/
#define CB_CFIG_TX_ADDR_WAKE BIT_0 /* Address Wakeup */
#define CB_DISABLE_MAGPAK_WAKE BIT_1 /* Magic Packet Wakeup disable */
/* Changed TX_FC_EN to TX_FC_DIS because 0 enables, 1 disables. Jul 8, 1999 */
#define CB_CFIG_TX_FC_DIS BIT_2 /* Tx Flow Control Disable */
#define CB_CFIG_FC_RESTOP BIT_3 /* Rx Flow Control Restop */
#define CB_CFIG_FC_RESTART BIT_4 /* Rx Flow Control Restart */
#define CB_CFIG_FC_REJECT BIT_5 /* Rx Flow Control Restart */
#define CB_CFIG_FC_OPTS (CB_CFIG_FC_RESTOP | CB_CFIG_FC_RESTART | CB_CFIG_FC_REJECT)
/* end 82558/9 specifics */
#define CB_CFIG_FORCE_FDX BIT_6 /* Force Full Duplex */
#define CB_CFIG_FDX_ENABLE BIT_7 /* Full Duplex Enabled */
/* byte 20 bit definitions*/
#define CB_CFIG_MULTI_IA BIT_6 /* Multiple IA Addr */
/* byte 21 bit definitions*/
#define CB_CFIG_MULTICAST_ALL BIT_3 /* Multicast All */
/* byte 22 bit defines */
#define CB_CFIG_RECEIVE_GAMLA_MODE BIT_0 /* D102 receive mode */
#define CB_CFIG_VLAN_DROP_ENABLE BIT_1 /* vlan stripping */
#define CB_CFIG_LONG_RX_OK BIT_3
/* function prototypes */
extern void e100_config_init(struct e100_private *bdp);
extern unsigned char e100_force_config(struct e100_private *bdp);
extern unsigned char e100_config(struct e100_private *bdp);
extern unsigned char e100_config_fc(struct e100_private *bdp);
extern void e100_config_promisc(struct e100_private *bdp, unsigned char enable);
extern void e100_config_brdcast_dsbl(struct e100_private *bdp);
extern void e100_config_mulcast_enbl(struct e100_private *bdp,
unsigned char enable);
extern void e100_config_ifs(struct e100_private *bdp);
extern void e100_config_force_dplx(struct e100_private *bdp);
#endif /* _E100_CONFIG_INC_ */
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/*******************************************************************************
This software program is available to you under a choice of one of two
licenses. You may choose to be licensed under either the GNU General Public
License (GPL) Version 2, June 1991, available at
http://www.fsf.org/copyleft/gpl.html, or the Intel BSD + Patent License, the
text of which follows:
Recipient has requested a license and Intel Corporation ("Intel") is willing
to grant a license for the software entitled Linux Base Driver for the
Intel(R) PRO/100 Family of Adapters (e100) (the "Software") being provided
by Intel Corporation. The following definitions apply to this license:
"Licensed Patents" means patent claims licensable by Intel Corporation which
are necessarily infringed by the use of sale of the Software alone or when
combined with the operating system referred to below.
"Recipient" means the party to whom Intel delivers this Software.
"Licensee" means Recipient and those third parties that receive a license to
any operating system available under the GNU Public License version 2.0 or
later.
Copyright (c) 1999 - 2002 Intel Corporation.
All rights reserved.
The license is provided to Recipient and Recipient's Licensees under the
following terms.
Redistribution and use in source and binary forms of the Software, with or
without modification, are permitted provided that the following conditions
are met:
Redistributions of source code of the Software may retain the above
copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form of the Software may reproduce the above
copyright notice, this list of conditions and the following disclaimer in
the documentation and/or materials provided with the distribution.
Neither the name of Intel Corporation nor the names of its contributors
shall be used to endorse or promote products derived from this Software
without specific prior written permission.
Intel hereby grants Recipient and Licensees a non-exclusive, worldwide,
royalty-free patent license under Licensed Patents to make, use, sell, offer
to sell, import and otherwise transfer the Software, if any, in source code
and object code form. This license shall include changes to the Software
that are error corrections or other minor changes to the Software that do
not add functionality or features when the Software is incorporated in any
version of an operating system that has been distributed under the GNU
General Public License 2.0 or later. This patent license shall apply to the
combination of the Software and any operating system licensed under the GNU
Public License version 2.0 or later if, at the time Intel provides the
Software to Recipient, such addition of the Software to the then publicly
available versions of such operating systems available under the GNU Public
License version 2.0 or later (whether in gold, beta or alpha form) causes
such combination to be covered by the Licensed Patents. The patent license
shall not apply to any other combinations which include the Software. NO
hardware per se is licensed hereunder.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR IT CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
ANY LOSS OF USE; DATA, OR PROFITS; OR BUSINESS INTERUPTION) HOWEVER CAUSED
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR
TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef _E100_PHY_INC_
#define _E100_PHY_INC_
#include "e100.h"
#include <linux/mii.h>
/*
* Auto-polarity enable/disable
* e100_autopolarity = 0 => disable auto-polarity
* e100_autopolarity = 1 => enable auto-polarity
* e100_autopolarity = 2 => let software determine
*/
#define E100_AUTOPOLARITY 2
#define IS_NC3133(bdp) (((bdp)->pdev->subsystem_vendor == 0x0E11) && \
((bdp)->pdev->subsystem_device == 0xB0E1))
#define PHY_503 0
#define PHY_100_A 0x000003E0
#define PHY_100_C 0x035002A8
#define PHY_NSC_TX 0x5c002000
#define PHY_82562ET 0x033002A8
#define PHY_82562EM 0x032002A8
#define PHY_82562EH 0x017002A8
#define PHY_82555_TX 0x015002a8 /* added this for 82555 */
#define PHY_OTHER 0xFFFF
#define MAX_PHY_ADDR 31
#define MIN_PHY_ADDR 0
#define PHY_MODEL_REV_ID_MASK 0xFFF0FFFF
#define PHY_DEFAULT_ADDRESS 1
#define PHY_ADDRESS_503 32
/* MDI Control register bit definitions */
#define MDI_PHY_READY BIT_28 /* PHY is ready for next MDI cycle */
#define MDI_NC3133_CONFIG_REG 0x19
#define MDI_NC3133_100FX_ENABLE BIT_2
#define MDI_NC3133_INT_ENABLE_REG 0x17
#define MDI_NC3133_INT_ENABLE BIT_1
/* MDI Control register opcode definitions */
#define MDI_WRITE 1 /* Phy Write */
#define MDI_READ 2 /* Phy read */
/* MDI register set*/
#define AUTO_NEG_NEXT_PAGE_REG 0x07 /* Auto-negotiation next page xmit */
#define EXTENDED_REG_0 0x10 /* Extended reg 0 (Phy 100 modes) */
#define EXTENDED_REG_1 0x14 /* Extended reg 1 (Phy 100 error indications) */
#define NSC_CONG_CONTROL_REG 0x17 /* National (TX) congestion control */
#define NSC_SPEED_IND_REG 0x19 /* National (TX) speed indication */
/* ############Start of 82555 specific defines################## */
/* Intel 82555 specific registers */
#define PHY_82555_CSR 0x10 /* 82555 CSR */
#define PHY_82555_SPECIAL_CONTROL 0x11 /* 82555 special control register */
#define PHY_82555_RCV_ERR 0x15 /* 82555 100BaseTx Receive Error
* Frame Counter */
#define PHY_82555_SYMBOL_ERR 0x16 /* 82555 RCV Symbol Error Counter */
#define PHY_82555_PREM_EOF_ERR 0x17 /* 82555 100BaseTx RCV Premature End
* of Frame Error Counter */
#define PHY_82555_EOF_COUNTER 0x18 /* 82555 end of frame error counter */
#define PHY_82555_MDI_EQUALIZER_CSR 0x1a /* 82555 specific equalizer reg. */
/* 82555 CSR bits */
#define PHY_82555_SPEED_BIT BIT_1
#define PHY_82555_POLARITY_BIT BIT_8
/* 82555 equalizer reg. opcodes */
#define ENABLE_ZERO_FORCING 0x2010 /* write to ASD conf. reg. 0 */
#define DISABLE_ZERO_FORCING 0x2000 /* write to ASD conf. reg. 0 */
/* 82555 special control reg. opcodes */
#define DISABLE_AUTO_POLARITY 0x0010
#define EXTENDED_SQUELCH_BIT BIT_2
/* ############End of 82555 specific defines##################### */
/* Auto-Negotiation advertisement register bit definitions*/
#define NWAY_AD_FC_SUPPORTED 0x0400 /* Flow Control supported */
/* Auto-Negotiation link partner ability register bit definitions*/
#define NWAY_LP_ABILITY 0x07e0 /* technologies supported */
/* PHY 100 Extended Register 0 bit definitions*/
#define PHY_100_ER0_FDX_INDIC BIT_0 /* 1 = FDX, 0 = half duplex */
#define PHY_100_ER0_SPEED_INDIC BIT_1 /* 1 = 100Mbps, 0= 10Mbps */
/* National Semiconductor TX phy congestion control register bit definitions*/
#define NSC_TX_CONG_TXREADY BIT_10 /* Makes TxReady an input */
#define NSC_TX_CONG_ENABLE BIT_8 /* Enables congestion control */
/* National Semiconductor TX phy speed indication register bit definitions*/
#define NSC_TX_SPD_INDC_SPEED BIT_6 /* 0 = 100Mbps, 1=10Mbps */
/************* function prototypes ************/
extern unsigned char e100_phy_init(struct e100_private *bdp);
extern unsigned char e100_update_link_state(struct e100_private *bdp);
extern unsigned char e100_phy_check(struct e100_private *bdp);
extern void e100_phy_set_speed_duplex(struct e100_private *bdp,
unsigned char force_restart);
extern void e100_phy_reset(struct e100_private *bdp);
extern void e100_mdi_write(struct e100_private *, u32, u32, u16);
extern void e100_mdi_read(struct e100_private *, u32, u32, u16 *);
#endif
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