Commit 18a9eae2 authored by Heiner Kallweit's avatar Heiner Kallweit Committed by David S. Miller

r8169: enable ASPM L0s state

ASPM is disabled completely because we've seen different types of
problems in the past. However it seems these problems occurred with
L1 or L1 sub-states only. On all the chip versions I've seen the
acceptable L0s exit latency is 512ns. This should be short enough not
to cause problems. If the actual L0s exit latency of the PCIe link
is bigger than 512ns then the PCI core will disable L0s anyway.
So let's give it a try and disable L1 and L1 sub-states only.
Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 7fb9b66d
...@@ -5281,11 +5281,10 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) ...@@ -5281,11 +5281,10 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
if (rc) if (rc)
return rc; return rc;
/* Disable ASPM completely as that cause random device stop working /* Disable ASPM L1 as that cause random device stop working
* problems as well as full system hangs for some PCIe devices users. * problems as well as full system hangs for some PCIe devices users.
*/ */
rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
PCIE_LINK_STATE_L1);
tp->aspm_manageable = !rc; tp->aspm_manageable = !rc;
/* enable device (incl. PCI PM wakeup and hotplug setup) */ /* enable device (incl. PCI PM wakeup and hotplug setup) */
......
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