mtd: spi-nor: Avoid setting SRWD bit in SR if WP# signal not connected
Setting the status register write disable (SRWD) bit in the status register (SR) with WP# signal of the flash left floating or wrongly tied to GND (that includes internal pull-downs), will configure the SR permanently as read-only. If WP# signal is left floating or wrongly tied to GND, avoid setting SRWD bit while writing the SR during flash protection. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230630142233.63585-3-amit.kumar-mahapatra@amd.comSigned-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
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