Commit 1928457e authored by Amit Daniel Kachhap's avatar Amit Daniel Kachhap Committed by Eduardo Valentin

thermal: exynos: Add hardware mode thermal calibration support

This patch adds support for h/w mode calibration in the TMU controller.
Soc's like 5440 support this features. The h/w bits needed for calibration
setting are same as that of enum calibration_type.
Acked-by: default avatarJonghwa Lee <jonghwa3.lee@samsung.com>
Acked-by: default avatarKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: default avatarAmit Daniel Kachhap <amit.daniel@samsung.com>
Signed-off-by: default avatarEduardo Valentin <eduardo.valentin@ti.com>
parent 5000806c
...@@ -73,6 +73,9 @@ static int temp_to_code(struct exynos_tmu_data *data, u8 temp) ...@@ -73,6 +73,9 @@ static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
struct exynos_tmu_platform_data *pdata = data->pdata; struct exynos_tmu_platform_data *pdata = data->pdata;
int temp_code; int temp_code;
if (pdata->cal_mode == HW_MODE)
return temp;
if (data->soc == SOC_ARCH_EXYNOS4210) if (data->soc == SOC_ARCH_EXYNOS4210)
/* temp should range between 25 and 125 */ /* temp should range between 25 and 125 */
if (temp < 25 || temp > 125) { if (temp < 25 || temp > 125) {
...@@ -107,6 +110,9 @@ static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code) ...@@ -107,6 +110,9 @@ static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
struct exynos_tmu_platform_data *pdata = data->pdata; struct exynos_tmu_platform_data *pdata = data->pdata;
int temp; int temp;
if (pdata->cal_mode == HW_MODE)
return temp_code;
if (data->soc == SOC_ARCH_EXYNOS4210) if (data->soc == SOC_ARCH_EXYNOS4210)
/* temp_code should range between 75 and 175 */ /* temp_code should range between 75 and 175 */
if (temp_code < 75 || temp_code > 175) { if (temp_code < 75 || temp_code > 175) {
...@@ -155,6 +161,9 @@ static int exynos_tmu_initialize(struct platform_device *pdev) ...@@ -155,6 +161,9 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
if (TMU_SUPPORTS(pdata, TRIM_RELOAD)) if (TMU_SUPPORTS(pdata, TRIM_RELOAD))
__raw_writel(1, data->base + reg->triminfo_ctrl); __raw_writel(1, data->base + reg->triminfo_ctrl);
if (pdata->cal_mode == HW_MODE)
goto skip_calib_data;
/* Save trimming info in order to perform calibration */ /* Save trimming info in order to perform calibration */
if (data->soc == SOC_ARCH_EXYNOS5440) { if (data->soc == SOC_ARCH_EXYNOS5440) {
/* /*
...@@ -190,6 +199,7 @@ static int exynos_tmu_initialize(struct platform_device *pdev) ...@@ -190,6 +199,7 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
(pdata->efuse_value >> reg->triminfo_85_shift) & (pdata->efuse_value >> reg->triminfo_85_shift) &
EXYNOS_TMU_TEMP_MASK; EXYNOS_TMU_TEMP_MASK;
skip_calib_data:
if (pdata->max_trigger_level > MAX_THRESHOLD_LEVS) { if (pdata->max_trigger_level > MAX_THRESHOLD_LEVS) {
dev_err(&pdev->dev, "Invalid max trigger level\n"); dev_err(&pdev->dev, "Invalid max trigger level\n");
goto out; goto out;
...@@ -297,7 +307,7 @@ static void exynos_tmu_control(struct platform_device *pdev, bool on) ...@@ -297,7 +307,7 @@ static void exynos_tmu_control(struct platform_device *pdev, bool on)
struct exynos_tmu_data *data = platform_get_drvdata(pdev); struct exynos_tmu_data *data = platform_get_drvdata(pdev);
struct exynos_tmu_platform_data *pdata = data->pdata; struct exynos_tmu_platform_data *pdata = data->pdata;
const struct exynos_tmu_registers *reg = pdata->registers; const struct exynos_tmu_registers *reg = pdata->registers;
unsigned int con, interrupt_en; unsigned int con, interrupt_en, cal_val;
mutex_lock(&data->lock); mutex_lock(&data->lock);
clk_enable(data->clk); clk_enable(data->clk);
...@@ -320,6 +330,27 @@ static void exynos_tmu_control(struct platform_device *pdev, bool on) ...@@ -320,6 +330,27 @@ static void exynos_tmu_control(struct platform_device *pdev, bool on)
con |= (pdata->noise_cancel_mode << reg->therm_trip_mode_shift); con |= (pdata->noise_cancel_mode << reg->therm_trip_mode_shift);
} }
if (pdata->cal_mode == HW_MODE) {
con &= ~(reg->calib_mode_mask << reg->calib_mode_shift);
cal_val = 0;
switch (pdata->cal_type) {
case TYPE_TWO_POINT_TRIMMING:
cal_val = 3;
break;
case TYPE_ONE_POINT_TRIMMING_85:
cal_val = 2;
break;
case TYPE_ONE_POINT_TRIMMING_25:
cal_val = 1;
break;
case TYPE_NONE:
break;
default:
dev_err(&pdev->dev, "Invalid calibration type, using none\n");
}
con |= cal_val << reg->calib_mode_shift;
}
if (on) { if (on) {
con |= (1 << reg->core_en_shift); con |= (1 << reg->core_en_shift);
interrupt_en = interrupt_en =
......
...@@ -28,6 +28,8 @@ ...@@ -28,6 +28,8 @@
enum calibration_type { enum calibration_type {
TYPE_ONE_POINT_TRIMMING, TYPE_ONE_POINT_TRIMMING,
TYPE_ONE_POINT_TRIMMING_25,
TYPE_ONE_POINT_TRIMMING_85,
TYPE_TWO_POINT_TRIMMING, TYPE_TWO_POINT_TRIMMING,
TYPE_NONE, TYPE_NONE,
}; };
...@@ -90,6 +92,10 @@ enum soc_type { ...@@ -90,6 +92,10 @@ enum soc_type {
* @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl * @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl
register. register.
* @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register. * @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register.
* @calib_mode_shift: shift bits of calibration mode value in tmu_ctrl
register.
* @calib_mode_mask: mask bits of calibration mode value in tmu_ctrl
register.
* @therm_trip_tq_en_shift: shift bits of thermal trip enable by TQ pin in * @therm_trip_tq_en_shift: shift bits of thermal trip enable by TQ pin in
tmu_ctrl register. tmu_ctrl register.
* @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register. * @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register.
...@@ -151,6 +157,8 @@ struct exynos_tmu_registers { ...@@ -151,6 +157,8 @@ struct exynos_tmu_registers {
u32 therm_trip_en_shift; u32 therm_trip_en_shift;
u32 buf_slope_sel_shift; u32 buf_slope_sel_shift;
u32 buf_slope_sel_mask; u32 buf_slope_sel_mask;
u32 calib_mode_shift;
u32 calib_mode_mask;
u32 therm_trip_tq_en_shift; u32 therm_trip_tq_en_shift;
u32 core_en_shift; u32 core_en_shift;
......
...@@ -189,6 +189,8 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = { ...@@ -189,6 +189,8 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT, .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT, .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK, .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
.calib_mode_shift = EXYNOS_TMU_CALIB_MODE_SHIFT,
.calib_mode_mask = EXYNOS_TMU_CALIB_MODE_MASK,
.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT, .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
.tmu_status = EXYNOS5440_TMU_S0_7_STATUS, .tmu_status = EXYNOS5440_TMU_S0_7_STATUS,
.tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP, .tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
......
...@@ -75,6 +75,8 @@ ...@@ -75,6 +75,8 @@
#define EXYNOS_TMU_TRIP_MODE_SHIFT 13 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13
#define EXYNOS_TMU_TRIP_MODE_MASK 0x7 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7
#define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
#define EXYNOS_TMU_CALIB_MODE_SHIFT 4
#define EXYNOS_TMU_CALIB_MODE_MASK 0x3
#define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0
#define EXYNOS_TMU_INTEN_RISE1_SHIFT 4 #define EXYNOS_TMU_INTEN_RISE1_SHIFT 4
......
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