Commit 1940075b authored by David S. Miller's avatar David S. Miller

Merge branch 'sh_eth-csum'

Sergei Shtylyov says:

====================
sh_eth: "intgelligent checksum" related cleanups

   Here's a set of 2 patches against DaveM's 'net.git' repo, as they are based
on a couple patches merged there recently; however, the patches are destined
for 'net-next.git' (once 'net.git' gets merged there next time). I'm cleaning
up the "intelligent checksum" related code (however, the driver only disables
this feature for now, theres's no proper offload supprt yet).
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents bb1d3034 62e04b7e
...@@ -535,9 +535,8 @@ static struct sh_eth_cpu_data r7s72100_data = { ...@@ -535,9 +535,8 @@ static struct sh_eth_cpu_data r7s72100_data = {
.rpadir_value = 2 << 16, .rpadir_value = 2 << 16,
.no_trimd = 1, .no_trimd = 1,
.no_ade = 1, .no_ade = 1,
.hw_crc = 1, .hw_checksum = 1,
.tsu = 1, .tsu = 1,
.shift_rd0 = 1,
}; };
static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
...@@ -574,10 +573,9 @@ static struct sh_eth_cpu_data r8a7740_data = { ...@@ -574,10 +573,9 @@ static struct sh_eth_cpu_data r8a7740_data = {
.rpadir_value = 2 << 16, .rpadir_value = 2 << 16,
.no_trimd = 1, .no_trimd = 1,
.no_ade = 1, .no_ade = 1,
.hw_crc = 1, .hw_checksum = 1,
.tsu = 1, .tsu = 1,
.select_mii = 1, .select_mii = 1,
.shift_rd0 = 1,
}; };
/* There is CPU dependent code */ /* There is CPU dependent code */
...@@ -814,9 +812,8 @@ static struct sh_eth_cpu_data sh7734_data = { ...@@ -814,9 +812,8 @@ static struct sh_eth_cpu_data sh7734_data = {
.no_trimd = 1, .no_trimd = 1,
.no_ade = 1, .no_ade = 1,
.tsu = 1, .tsu = 1,
.hw_crc = 1, .hw_checksum = 1,
.select_mii = 1, .select_mii = 1,
.shift_rd0 = 1,
}; };
/* SH7763 */ /* SH7763 */
...@@ -931,7 +928,7 @@ static int sh_eth_reset(struct net_device *ndev) ...@@ -931,7 +928,7 @@ static int sh_eth_reset(struct net_device *ndev)
sh_eth_write(ndev, 0x0, RDFFR); sh_eth_write(ndev, 0x0, RDFFR);
/* Reset HW CRC register */ /* Reset HW CRC register */
if (mdp->cd->hw_crc) if (mdp->cd->hw_checksum)
sh_eth_write(ndev, 0x0, CSMR); sh_eth_write(ndev, 0x0, CSMR);
/* Select MII mode */ /* Select MII mode */
...@@ -1416,7 +1413,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) ...@@ -1416,7 +1413,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
* the RFS bits are from bit 25 to bit 16. So, the * the RFS bits are from bit 25 to bit 16. So, the
* driver needs right shifting by 16. * driver needs right shifting by 16.
*/ */
if (mdp->cd->shift_rd0) if (mdp->cd->hw_checksum)
desc_status >>= 16; desc_status >>= 16;
skb = mdp->rx_skbuff[entry]; skb = mdp->rx_skbuff[entry];
...@@ -1990,7 +1987,7 @@ static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) ...@@ -1990,7 +1987,7 @@ static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
add_reg(MAFCR); add_reg(MAFCR);
if (cd->rtrate) if (cd->rtrate)
add_reg(RTRATE); add_reg(RTRATE);
if (cd->hw_crc) if (cd->hw_checksum)
add_reg(CSMR); add_reg(CSMR);
if (cd->select_mii) if (cd->select_mii)
add_reg(RMII_MII); add_reg(RMII_MII);
......
...@@ -488,9 +488,8 @@ struct sh_eth_cpu_data { ...@@ -488,9 +488,8 @@ struct sh_eth_cpu_data {
unsigned rpadir:1; /* E-DMAC have RPADIR */ unsigned rpadir:1; /* E-DMAC have RPADIR */
unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */ unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */
unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */ unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */
unsigned hw_crc:1; /* E-DMAC have CSMR */ unsigned hw_checksum:1; /* E-DMAC has CSMR */
unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */ unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */
unsigned shift_rd0:1; /* shift Rx descriptor word 0 right by 16 */
unsigned rmiimode:1; /* EtherC has RMIIMODE register */ unsigned rmiimode:1; /* EtherC has RMIIMODE register */
unsigned rtrate:1; /* EtherC has RTRATE register */ unsigned rtrate:1; /* EtherC has RTRATE register */
}; };
......
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