Commit 1948d5c5 authored by Rahul Tanwar's avatar Rahul Tanwar Committed by Linus Walleij

pinctrl: Add pinmux & GPIO controller driver for a new SoC

Intel Lightning Mountain SoC has a pinmux controller & GPIO controller IP which
controls pin multiplexing & configuration including GPIO functions selection &
GPIO attributes configuration.

This IP is not based on & does not have anything in common with Chassis
specification. The pinctrl drivers under pinctrl/intel/* are all based upon
Chassis spec compliant pinctrl IPs. So this driver doesn't fit & can not use
pinctrl framework under pinctrl/intel/* and it requires a separate new driver.

Add a new GPIO & pin control framework based driver for this IP.
Signed-off-by: default avatarRahul Tanwar <rahul.tanwar@linux.intel.com>
Link: https://lore.kernel.org/r/33e649758b70490f01724a887c490d5008c7656d.1573797249.git.rahul.tanwar@linux.intel.comReviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 54787d7c
...@@ -420,4 +420,22 @@ config PINCTRL_TB10X ...@@ -420,4 +420,22 @@ config PINCTRL_TB10X
depends on OF && ARC_PLAT_TB10X depends on OF && ARC_PLAT_TB10X
select GPIOLIB select GPIOLIB
config PINCTRL_EQUILIBRIUM
tristate "Generic pinctrl and GPIO driver for Intel Lightning Mountain SoC"
select PINMUX
select PINCONF
select GPIOLIB
select GPIO_GENERIC
select GPIOLIB_IRQCHIP
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
help
Equilibrium pinctrl driver is a pinctrl & GPIO driver for Intel Lightning
Mountain network processor SoC that supports both the linux GPIO and pin
control frameworks. It provides interfaces to setup pinmux, assign desired
pin functions, configure GPIO attributes for LGM SoC pins. Pinmux and
pinconf settings are retrieved from device tree.
endif endif
...@@ -46,6 +46,7 @@ obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o ...@@ -46,6 +46,7 @@ obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o
obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o
obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o
obj-y += actions/ obj-y += actions/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
......
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright(c) 2019 Intel Corporation.
*/
#ifndef __PINCTRL_EQUILIBRIUM_H
#define __PINCTRL_EQUILIBRIUM_H
/* PINPAD register offset */
#define REG_PMX_BASE 0x0 /* Port Multiplexer Control Register */
#define REG_PUEN 0x80 /* PULL UP Enable Register */
#define REG_PDEN 0x84 /* PULL DOWN Enable Register */
#define REG_SRC 0x88 /* Slew Rate Control Register */
#define REG_DCC0 0x8C /* Drive Current Control Register 0 */
#define REG_DCC1 0x90 /* Drive Current Control Register 1 */
#define REG_OD 0x94 /* Open Drain Enable Register */
#define REG_AVAIL 0x98 /* Pad Control Availability Register */
#define DRV_CUR_PINS 16 /* Drive Current pin number per register */
#define REG_DRCC(x) (REG_DCC0 + (x) * 4) /* Driver current macro */
/* GPIO register offset */
#define GPIO_OUT 0x0 /* Data Output Register */
#define GPIO_IN 0x4 /* Data Input Register */
#define GPIO_DIR 0x8 /* Direction Register */
#define GPIO_EXINTCR0 0x18 /* External Interrupt Control Register 0 */
#define GPIO_EXINTCR1 0x1C /* External Interrupt Control Register 1 */
#define GPIO_IRNCR 0x20 /* IRN Capture Register */
#define GPIO_IRNICR 0x24 /* IRN Interrupt Control Register */
#define GPIO_IRNEN 0x28 /* IRN Interrupt Enable Register */
#define GPIO_IRNCFG 0x2C /* IRN Interrupt Configuration Register */
#define GPIO_IRNRNSET 0x30 /* IRN Interrupt Enable Set Register */
#define GPIO_IRNENCLR 0x34 /* IRN Interrupt Enable Clear Register */
#define GPIO_OUTSET 0x40 /* Output Set Register */
#define GPIO_OUTCLR 0x44 /* Output Clear Register */
#define GPIO_DIRSET 0x48 /* Direction Set Register */
#define GPIO_DIRCLR 0x4C /* Direction Clear Register */
/* parse given pin's driver current value */
#define PARSE_DRV_CURRENT(val, pin) (((val) >> ((pin) * 2)) & 0x3)
#define GPIO_EDGE_TRIG 0
#define GPIO_LEVEL_TRIG 1
#define GPIO_SINGLE_EDGE 0
#define GPIO_BOTH_EDGE 1
#define GPIO_POSITIVE_TRIG 0
#define GPIO_NEGATIVE_TRIG 1
#define EQBR_GPIO_MODE 0
typedef enum {
OP_COUNT_NR_FUNCS,
OP_ADD_FUNCS,
OP_COUNT_NR_FUNC_GRPS,
OP_ADD_FUNC_GRPS,
OP_NONE,
} funcs_util_ops;
/**
* struct gpio_irq_type: gpio irq configuration
* @trig_type: level trigger or edge trigger
* @edge_type: sigle edge or both edge
* @logic_type: positive trigger or negative trigger
*/
struct gpio_irq_type {
unsigned int trig_type;
unsigned int edge_type;
unsigned int logic_type;
};
/**
* struct eqbr_pmx_func: represent a pin function.
* @name: name of the pin function, used to lookup the function.
* @groups: one or more names of pin groups that provide this function.
* @nr_groups: number of groups included in @groups.
*/
struct eqbr_pmx_func {
const char *name;
const char **groups;
unsigned int nr_groups;
};
/**
* struct eqbr_pin_bank: represent a pin bank.
* @membase: base address of the pin bank register.
* @id: bank id, to idenify the unique bank.
* @pin_base: starting pin number of the pin bank.
* @nr_pins: number of the pins of the pin bank.
* @aval_pinmap: available pin bitmap of the pin bank.
*/
struct eqbr_pin_bank {
void __iomem *membase;
unsigned int id;
unsigned int pin_base;
unsigned int nr_pins;
u32 aval_pinmap;
};
/**
* struct eqbr_gpio_ctrl: represent a gpio controller.
* @node: device node of gpio controller.
* @bank: pointer to corresponding pin bank.
* @membase: base address of the gpio controller.
* @chip: gpio chip.
* @ic: irq chip.
* @name: gpio chip name.
* @virq: irq number of the gpio chip to parent's irq domain.
* @lock: spin lock to protect gpio register write.
*/
struct eqbr_gpio_ctrl {
struct device_node *node;
struct eqbr_pin_bank *bank;
void __iomem *membase;
struct gpio_chip chip;
struct irq_chip ic;
const char *name;
unsigned int virq;
raw_spinlock_t lock; /* protect gpio register */
};
/**
* struct eqbr_pinctrl_drv_data:
* @dev: device instance representing the controller.
* @pctl_desc: pin controller descriptor.
* @pctl_dev: pin control class device
* @membase: base address of pin controller
* @pin_banks: list of pin banks of the driver.
* @nr_banks: number of pin banks.
* @gpio_ctrls: list of gpio controllers.
* @nr_gpio_ctrls: number of gpio controllers.
* @lock: protect pinctrl register write
*/
struct eqbr_pinctrl_drv_data {
struct device *dev;
struct pinctrl_desc pctl_desc;
struct pinctrl_dev *pctl_dev;
void __iomem *membase;
struct eqbr_pin_bank *pin_banks;
unsigned int nr_banks;
struct eqbr_gpio_ctrl *gpio_ctrls;
unsigned int nr_gpio_ctrls;
raw_spinlock_t lock; /* protect pinpad register */
};
#endif /* __PINCTRL_EQUILIBRIUM_H */
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