MIPS: Octeon: Support 256 MSI on PCIe

Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1507/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: Octeon: Support 256 MSI on PCIe
Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1507/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
1aa2b278 · David Daney · Ralf Baechle · 0c2f4551 · 1aa2b278 · 1aa2b278
Commit 1aa2b278 authored Jul 26, 2010 by David Daney Committed by Ralf Baechle Aug 05, 2010
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arch/mips/include/asm/mach-cavium-octeon/irq.h arch/mips/include/asm/mach-cavium-octeon/irq.h +1 -1

arch/mips/pci/msi-octeon.c arch/mips/pci/msi-octeon.c +177 -117

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--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -172,7 +172,7 @@
 #ifdef CONFIG_PCI_MSI
 /* 152 - 215 represent the MSI interrupts 0-63 */
 #define OCTEON_IRQ_MSI_BIT0	152
-#define OCTEON_IRQ_MSI_LAST	(OCTEON_IRQ_MSI_BIT0 + 63)
+#define OCTEON_IRQ_MSI_LAST	(OCTEON_IRQ_MSI_BIT0 + 255)
 #define OCTEON_IRQ_LAST		(OCTEON_IRQ_MSI_LAST + 1)
 #else

--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c