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Commit 1aa8e847 authored by Sujith's avatar Sujith Committed by John W. Linville
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ath9k: Remove has_hw_phycounters 

PHY counters are available in all chipsets supported
by ath9k. Remove the check.
Signed-off-by: default avatarSujith <Sujith.Manoharan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 2a219eb2
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Showing with 88 additions and 112 deletions
drivers/net/wireless/ath/ath9k/ani.c
View file @ 1aa8e847
...@@ -236,36 +236,35 @@ static void ath9k_ani_restart(struct ath_hw *ah) ...@@ -236,36 +236,35 @@ static void ath9k_ani_restart(struct ath_hw *ah)
return; return;
aniState = ah->curani; aniState = ah->curani;
aniState->listenTime = 0; aniState->listenTime = 0;
if (ah->has_hw_phycounters) {
if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
aniState->ofdmPhyErrBase = 0; aniState->ofdmPhyErrBase = 0;
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"OFDM Trigger is too high for hw counters\n");
} else {
aniState->ofdmPhyErrBase =
AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
}
if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
aniState->cckPhyErrBase = 0;
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"CCK Trigger is too high for hw counters\n");
} else {
aniState->cckPhyErrBase =
AR_PHY_COUNTMAX - aniState->cckTrigHigh;
}
DPRINTF(ah->ah_sc, ATH_DBG_ANI, DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"Writing ofdmbase=%u cckbase=%u\n", "OFDM Trigger is too high for hw counters\n");
aniState->ofdmPhyErrBase, } else {
aniState->cckPhyErrBase); aniState->ofdmPhyErrBase =
REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase); AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase); }
REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); aniState->cckPhyErrBase = 0;
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); "CCK Trigger is too high for hw counters\n");
} else {
aniState->cckPhyErrBase =
AR_PHY_COUNTMAX - aniState->cckTrigHigh;
} }
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"Writing ofdmbase=%u cckbase=%u\n",
aniState->ofdmPhyErrBase,
aniState->cckPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
aniState->ofdmPhyErrCount = 0; aniState->ofdmPhyErrCount = 0;
aniState->cckPhyErrCount = 0; aniState->cckPhyErrCount = 0;
} }
...@@ -530,18 +529,12 @@ void ath9k_ani_reset(struct ath_hw *ah) ...@@ -530,18 +529,12 @@ void ath9k_ani_reset(struct ath_hw *ah)
if (aniState->firstepLevel != 0) if (aniState->firstepLevel != 0)
ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
aniState->firstepLevel); aniState->firstepLevel);
if (ah->has_hw_phycounters) {
ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
~ATH9K_RX_FILTER_PHYERR);
ath9k_ani_restart(ah);
REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
} else { ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
ath9k_ani_restart(ah); ~ATH9K_RX_FILTER_PHYERR);
ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) | ath9k_ani_restart(ah);
ATH9K_RX_FILTER_PHYERR); REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
} REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
} }
void ath9k_hw_ani_monitor(struct ath_hw *ah, void ath9k_hw_ani_monitor(struct ath_hw *ah,
...@@ -550,6 +543,8 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, ...@@ -550,6 +543,8 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
{ {
struct ar5416AniState *aniState; struct ar5416AniState *aniState;
int32_t listenTime; int32_t listenTime;
u32 phyCnt1, phyCnt2;
u32 ofdmPhyErrCnt, cckPhyErrCnt;
if (!DO_ANI(ah)) if (!DO_ANI(ah))
return; return;
...@@ -566,50 +561,45 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, ...@@ -566,50 +561,45 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
aniState->listenTime += listenTime; aniState->listenTime += listenTime;
if (ah->has_hw_phycounters) { ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
u32 phyCnt1, phyCnt2;
u32 ofdmPhyErrCnt, cckPhyErrCnt;
ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); if (phyCnt1 < aniState->ofdmPhyErrBase ||
phyCnt2 < aniState->cckPhyErrBase) {
if (phyCnt1 < aniState->ofdmPhyErrBase || if (phyCnt1 < aniState->ofdmPhyErrBase) {
phyCnt2 < aniState->cckPhyErrBase) { DPRINTF(ah->ah_sc, ATH_DBG_ANI,
if (phyCnt1 < aniState->ofdmPhyErrBase) { "phyCnt1 0x%x, resetting "
DPRINTF(ah->ah_sc, ATH_DBG_ANI, "counter value to 0x%x\n",
"phyCnt1 0x%x, resetting " phyCnt1, aniState->ofdmPhyErrBase);
"counter value to 0x%x\n", REG_WRITE(ah, AR_PHY_ERR_1,
phyCnt1, aniState->ofdmPhyErrBase); aniState->ofdmPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_1, REG_WRITE(ah, AR_PHY_ERR_MASK_1,
aniState->ofdmPhyErrBase); AR_PHY_ERR_OFDM_TIMING);
REG_WRITE(ah, AR_PHY_ERR_MASK_1, }
AR_PHY_ERR_OFDM_TIMING); if (phyCnt2 < aniState->cckPhyErrBase) {
} DPRINTF(ah->ah_sc, ATH_DBG_ANI,
if (phyCnt2 < aniState->cckPhyErrBase) { "phyCnt2 0x%x, resetting "
DPRINTF(ah->ah_sc, ATH_DBG_ANI, "counter value to 0x%x\n",
"phyCnt2 0x%x, resetting " phyCnt2, aniState->cckPhyErrBase);
"counter value to 0x%x\n", REG_WRITE(ah, AR_PHY_ERR_2,
phyCnt2, aniState->cckPhyErrBase); aniState->cckPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_2, REG_WRITE(ah, AR_PHY_ERR_MASK_2,
aniState->cckPhyErrBase); AR_PHY_ERR_CCK_TIMING);
REG_WRITE(ah, AR_PHY_ERR_MASK_2,
AR_PHY_ERR_CCK_TIMING);
}
return;
} }
return;
}
ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
ah->stats.ast_ani_ofdmerrs += ah->stats.ast_ani_ofdmerrs +=
ofdmPhyErrCnt - aniState->ofdmPhyErrCount; ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
aniState->ofdmPhyErrCount = ofdmPhyErrCnt; aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
ah->stats.ast_ani_cckerrs += ah->stats.ast_ani_cckerrs +=
cckPhyErrCnt - aniState->cckPhyErrCount; cckPhyErrCnt - aniState->cckPhyErrCount;
aniState->cckPhyErrCount = cckPhyErrCnt; aniState->cckPhyErrCount = cckPhyErrCnt;
}
if (aniState->listenTime > 5 * ah->aniperiod) { if (aniState->listenTime > 5 * ah->aniperiod) {
if (aniState->ofdmPhyErrCount <= aniState->listenTime * if (aniState->ofdmPhyErrCount <= aniState->listenTime *
...@@ -632,11 +622,6 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, ...@@ -632,11 +622,6 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
} }
} }
bool ath9k_hw_phycounters(struct ath_hw *ah)
{
return ah->has_hw_phycounters ? true : false;
}
void ath9k_enable_mib_counters(struct ath_hw *ah) void ath9k_enable_mib_counters(struct ath_hw *ah)
{ {
DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n"); DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n");
...@@ -781,9 +766,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah) ...@@ -781,9 +766,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
{ {
int i; int i;
DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n"); DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Initialize ANI\n");
ah->has_hw_phycounters = 1;
memset(ah->ani, 0, sizeof(ah->ani)); memset(ah->ani, 0, sizeof(ah->ani));
for (i = 0; i < ARRAY_SIZE(ah->ani); i++) { for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
...@@ -799,24 +782,22 @@ void ath9k_hw_ani_init(struct ath_hw *ah) ...@@ -799,24 +782,22 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
ATH9K_ANI_CCK_WEAK_SIG_THR; ATH9K_ANI_CCK_WEAK_SIG_THR;
ah->ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; ah->ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
if (ah->has_hw_phycounters) { ah->ani[i].ofdmPhyErrBase =
ah->ani[i].ofdmPhyErrBase = AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH; ah->ani[i].cckPhyErrBase =
ah->ani[i].cckPhyErrBase = AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
}
}
if (ah->has_hw_phycounters) {
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"Setting OfdmErrBase = 0x%08x\n",
ah->ani[0].ofdmPhyErrBase);
DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
ah->ani[0].cckPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
ath9k_enable_mib_counters(ah);
} }
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"Setting OfdmErrBase = 0x%08x\n",
ah->ani[0].ofdmPhyErrBase);
DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
ah->ani[0].cckPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
ath9k_enable_mib_counters(ah);
ah->aniperiod = ATH9K_ANI_PERIOD; ah->aniperiod = ATH9K_ANI_PERIOD;
if (ah->config.enable_ani) if (ah->config.enable_ani)
ah->proc_phyerr |= HAL_PROCESS_ANI; ah->proc_phyerr |= HAL_PROCESS_ANI;
...@@ -826,9 +807,7 @@ void ath9k_hw_ani_disable(struct ath_hw *ah) ...@@ -826,9 +807,7 @@ void ath9k_hw_ani_disable(struct ath_hw *ah)
{ {
DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling ANI\n"); DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling ANI\n");
if (ah->has_hw_phycounters) { ath9k_hw_disable_mib_counters(ah);
ath9k_hw_disable_mib_counters(ah); REG_WRITE(ah, AR_PHY_ERR_1, 0);
REG_WRITE(ah, AR_PHY_ERR_1, 0); REG_WRITE(ah, AR_PHY_ERR_2, 0);
REG_WRITE(ah, AR_PHY_ERR_2, 0);
}
} }
drivers/net/wireless/ath/ath9k/ani.h
View file @ 1aa8e847
...@@ -124,7 +124,6 @@ void ath9k_ani_reset(struct ath_hw *ah); ...@@ -124,7 +124,6 @@ void ath9k_ani_reset(struct ath_hw *ah);
void ath9k_hw_ani_monitor(struct ath_hw *ah, void ath9k_hw_ani_monitor(struct ath_hw *ah,
const struct ath9k_node_stats *stats, const struct ath9k_node_stats *stats,
struct ath9k_channel *chan); struct ath9k_channel *chan);
bool ath9k_hw_phycounters(struct ath_hw *ah);
void ath9k_enable_mib_counters(struct ath_hw *ah); void ath9k_enable_mib_counters(struct ath_hw *ah);
void ath9k_hw_disable_mib_counters(struct ath_hw *ah); void ath9k_hw_disable_mib_counters(struct ath_hw *ah);
u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt, u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt,
......
drivers/net/wireless/ath/ath9k/hw.h
View file @ 1aa8e847
...@@ -507,7 +507,6 @@ struct ath_hw { ...@@ -507,7 +507,6 @@ struct ath_hw {
/* ANI */ /* ANI */
u32 proc_phyerr; u32 proc_phyerr;
bool has_hw_phycounters;
u32 aniperiod; u32 aniperiod;
struct ar5416AniState *curani; struct ar5416AniState *curani;
struct ar5416AniState ani[255]; struct ar5416AniState ani[255];
......
drivers/net/wireless/ath/ath9k/main.c
View file @ 1aa8e847
...@@ -2214,8 +2214,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw, ...@@ -2214,8 +2214,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
if ((conf->type == NL80211_IFTYPE_STATION) || if ((conf->type == NL80211_IFTYPE_STATION) ||
(conf->type == NL80211_IFTYPE_ADHOC) || (conf->type == NL80211_IFTYPE_ADHOC) ||
(conf->type == NL80211_IFTYPE_MESH_POINT)) { (conf->type == NL80211_IFTYPE_MESH_POINT)) {
if (ath9k_hw_phycounters(sc->sc_ah)) sc->imask |= ATH9K_INT_MIB;
sc->imask |= ATH9K_INT_MIB;
sc->imask |= ATH9K_INT_TSFOOR; sc->imask |= ATH9K_INT_TSFOOR;
} }
......
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