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Commit 1b00767f authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
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MIPS: Remove PMC MSP71xx platform 

No (active) developer owns this hardware, so let's remove Linux support.
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 10760dde
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arch/mips/Kbuild.platforms
View file @ 1b00767f
......@@ -24,7 +24,6 @@ platforms += netlogic
platforms += paravirt
platforms += pic32
platforms += pistachio
platforms += pmcs-msp71xx
platforms += pnx833x
platforms += ralink
platforms += rb532
......
arch/mips/Kconfig
View file @ 1b00767f
......@@ -608,30 +608,6 @@ config NXP_STB225
help
Support for NXP Semiconductors STB225 Development Board.
config PMC_MSP
bool "PMC-Sierra MSP chipsets"
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select SWAP_IO_SPACE
select NO_EXCEPT_FILL
select BOOT_RAW
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_MIPS16
select IRQ_MIPS_CPU
select SERIAL_8250
select SERIAL_8250_CONSOLE
select USB_EHCI_BIG_ENDIAN_MMIO
select USB_EHCI_BIG_ENDIAN_DESC
help
This adds support for the PMC-Sierra family of Multi-Service
Processor System-On-A-Chips. These parts include a number
of integrated peripherals, interfaces and DSPs in addition to
a variety of MIPS cores.
config RALINK
bool "Ralink based machines"
select CEVT_R4K
......@@ -1076,7 +1052,6 @@ source "arch/mips/jz4740/Kconfig"
source "arch/mips/lantiq/Kconfig"
source "arch/mips/pic32/Kconfig"
source "arch/mips/pistachio/Kconfig"
source "arch/mips/pmcs-msp71xx/Kconfig"
source "arch/mips/ralink/Kconfig"
source "arch/mips/sgi-ip27/Kconfig"
source "arch/mips/sibyte/Kconfig"
......
arch/mips/configs/msp71xx_defconfig deleted 100644 → 0
View file @ 10760dde
CONFIG_LOCALVERSION="-pmc"
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_PREEMPT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
# CONFIG_SHMEM is not set
CONFIG_SLAB=y
CONFIG_PMC_MSP=y
CONFIG_PMC_MSP7120_GW=y
CONFIG_CPU_MIPS32_R2=y
CONFIG_NR_CPUS=2
CONFIG_PCI=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_NET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_INET_AH=y
CONFIG_INET_ESP=y
CONFIG_INET_IPCOMP=y
# CONFIG_IPV6 is not set
CONFIG_NETFILTER=y
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_BRIDGE=y
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_RAM=y
CONFIG_MTD_PMC_MSP_EVM=y
CONFIG_BLK_DEV_RAM=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_PPP=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_PMCMSP=y
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_MON=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
CONFIG_USB_STORAGE=y
CONFIG_EXT2_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_JFFS2_FS=y
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_MAGIC_SYSRQ=y
arch/mips/include/asm/bootinfo.h
View file @ 1b00767f
......@@ -41,17 +41,6 @@
#define MACH_DS5800 9 /* DECsystem 5800 */
#define MACH_DS5900 10 /* DECsystem 5900 */
/*
* Valid machtype for group PMC-MSP
*/
#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */
#define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */
#define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */
#define MACH_MSP7120_EVAL 3 /* PMC-Sierra MSP7120 Evaluation */
#define MACH_MSP7120_GW 4 /* PMC-Sierra MSP7120 Residential GW */
#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
/*
* Valid machtype for group Mikrotik
*/
......
arch/mips/include/asm/mach-pmcs-msp71xx/cpu-feature-overrides.h deleted 100644 → 0
View file @ 10760dde
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
*/
#ifndef __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H
#define cpu_has_mips16 1
#define cpu_has_dsp 1
/* #define cpu_has_dsp2 ??? - do runtime detection */
#define cpu_has_mipsmt 1
#define cpu_has_fpu 0
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 1
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#endif /* __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H */
arch/mips/include/asm/mach-pmcs-msp71xx/msp_cic_int.h deleted 100644 → 0
View file @ 10760dde
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Defines for the MSP interrupt controller.
*
* Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
* Author: Carsten Langgaard, carstenl@mips.com
*
* ########################################################################
*
* ########################################################################
*/
#ifndef _MSP_CIC_INT_H
#define _MSP_CIC_INT_H
/*
* The PMC-Sierra CIC interrupts are all centrally managed by the
* CIC sub-system.
* We attempt to keep the interrupt numbers as consistent as possible
* across all of the MSP devices, but some differences will creep in ...
* The interrupts which are directly forwarded to the MIPS core interrupts
* are assigned interrupts in the range 0-7, interrupts cascaded through
* the CIC are assigned interrupts 8-39. The cascade occurs on C_IRQ4
* (MSP_INT_CIC). Currently we don't really distinguish between VPE1
* and VPE0 (or thread contexts for that matter). Will have to fix.
* The PER interrupts are assigned interrupts in the range 40-71.
*/
/*
* IRQs directly forwarded to the CPU
*/
#define MSP_MIPS_INTBASE 0
#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
#define MSP_INT_USB 4 /* IRQ for USB, C_IRQ2 */
#define MSP_INT_SAR 5 /* IRQ for ADSL2+ SAR, C_IRQ3 */
#define MSP_INT_CIC 6 /* IRQ for CIC block, C_IRQ4 */
#define MSP_INT_SEC 7 /* IRQ for Sec engine, C_IRQ5 */
/*
* IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
* These defines should be tied to the register definitions for the CIC
* interrupt routine. For now, just use hard-coded values.
*/
#define MSP_CIC_INTBASE (MSP_MIPS_INTBASE + 8)
#define MSP_INT_EXT0 (MSP_CIC_INTBASE + 0)
/* External interrupt 0 */
#define MSP_INT_EXT1 (MSP_CIC_INTBASE + 1)
/* External interrupt 1 */
#define MSP_INT_EXT2 (MSP_CIC_INTBASE + 2)
/* External interrupt 2 */
#define MSP_INT_EXT3 (MSP_CIC_INTBASE + 3)
/* External interrupt 3 */
#define MSP_INT_CPUIF (MSP_CIC_INTBASE + 4)
/* CPU interface interrupt */
#define MSP_INT_EXT4 (MSP_CIC_INTBASE + 5)
/* External interrupt 4 */
#define MSP_INT_CIC_USB (MSP_CIC_INTBASE + 6)
/* Cascaded IRQ for USB */
#define MSP_INT_MBOX (MSP_CIC_INTBASE + 7)
/* Sec engine mailbox IRQ */
#define MSP_INT_EXT5 (MSP_CIC_INTBASE + 8)
/* External interrupt 5 */
#define MSP_INT_TDM (MSP_CIC_INTBASE + 9)
/* TDM interrupt */
#define MSP_INT_CIC_MAC0 (MSP_CIC_INTBASE + 10)
/* Cascaded IRQ for MAC 0 */
#define MSP_INT_CIC_MAC1 (MSP_CIC_INTBASE + 11)
/* Cascaded IRQ for MAC 1 */
#define MSP_INT_CIC_SEC (MSP_CIC_INTBASE + 12)
/* Cascaded IRQ for sec engine */
#define MSP_INT_PER (MSP_CIC_INTBASE + 13)
/* Peripheral interrupt */
#define MSP_INT_TIMER0 (MSP_CIC_INTBASE + 14)
/* SLP timer 0 */
#define MSP_INT_TIMER1 (MSP_CIC_INTBASE + 15)
/* SLP timer 1 */
#define MSP_INT_TIMER2 (MSP_CIC_INTBASE + 16)
/* SLP timer 2 */
#define MSP_INT_VPE0_TIMER (MSP_CIC_INTBASE + 17)
/* VPE0 MIPS timer */
#define MSP_INT_BLKCP (MSP_CIC_INTBASE + 18)
/* Block Copy */
#define MSP_INT_UART0 (MSP_CIC_INTBASE + 19)
/* UART 0 */
#define MSP_INT_PCI (MSP_CIC_INTBASE + 20)
/* PCI subsystem */
#define MSP_INT_EXT6 (MSP_CIC_INTBASE + 21)
/* External interrupt 5 */
#define MSP_INT_PCI_MSI (MSP_CIC_INTBASE + 22)
/* PCI Message Signal */
#define MSP_INT_CIC_SAR (MSP_CIC_INTBASE + 23)
/* Cascaded ADSL2+ SAR IRQ */
#define MSP_INT_DSL (MSP_CIC_INTBASE + 24)
/* ADSL2+ IRQ */
#define MSP_INT_CIC_ERR (MSP_CIC_INTBASE + 25)
/* SLP error condition */
#define MSP_INT_VPE1_TIMER (MSP_CIC_INTBASE + 26)
/* VPE1 MIPS timer */
#define MSP_INT_VPE0_PC (MSP_CIC_INTBASE + 27)
/* VPE0 Performance counter */
#define MSP_INT_VPE1_PC (MSP_CIC_INTBASE + 28)
/* VPE1 Performance counter */
#define MSP_INT_EXT7 (MSP_CIC_INTBASE + 29)
/* External interrupt 5 */
#define MSP_INT_VPE0_SW (MSP_CIC_INTBASE + 30)
/* VPE0 Software interrupt */
#define MSP_INT_VPE1_SW (MSP_CIC_INTBASE + 31)
/* VPE0 Software interrupt */
/*
* IRQs cascaded on CIC PER interrupt (MSP_INT_PER)
*/
#define MSP_PER_INTBASE (MSP_CIC_INTBASE + 32)
/* Reserved 0-1 */
#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
/* UART 1 */
/* Reserved 3-5 */
#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
/* 2-wire */
#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
/* Peripheral timer block out 0 */
#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
/* Peripheral timer block out 1 */
/* Reserved 9 */
#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
/* SPI RX complete */
#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
/* SPI TX complete */
#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
/* GPIO */
#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
/* Peripheral error */
/* Reserved 14-31 */
#endif /* !_MSP_CIC_INT_H */
arch/mips/include/asm/mach-pmcs-msp71xx/msp_int.h deleted 100644 → 0
View file @ 10760dde
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Defines for the MSP interrupt handlers.
*
* Copyright (C) 2005, PMC-Sierra, Inc. All rights reserved.
* Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
*
* ########################################################################
*
* ########################################################################
*/
#ifndef _MSP_INT_H
#define _MSP_INT_H
/*
* The PMC-Sierra MSP product line has at least two different interrupt
* controllers, the SLP register based scheme and the CIC interrupt
* controller block mechanism. This file distinguishes between them
* so that devices see a uniform interface.
*/
#if defined(CONFIG_IRQ_MSP_SLP)
#include "msp_slp_int.h"
#elif defined(CONFIG_IRQ_MSP_CIC)
#include "msp_cic_int.h"
#else
#error "What sort of interrupt controller does *your* MSP have?"
#endif
#endif /* !_MSP_INT_H */
arch/mips/include/asm/mach-pmcs-msp71xx/msp_pci.h deleted 100644 → 0
View file @ 10760dde
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2000-2006 PMC-Sierra INC.
*
* PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
* SOFTWARE.
*/
#ifndef _MSP_PCI_H_
#define _MSP_PCI_H_
#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220))
/*
* It is convenient to program the OATRAN register so that
* Athena virtual address space and PCI address space are
* the same. This is not a requirement, just a convenience.
*
* The only hard restrictions on the value of OATRAN is that
* OATRAN must not be programmed to allow translated memory
* addresses to fall within the lowest 512MB of
* PCI address space. This region is hardcoded
* for use as Athena PCI Host Controller target
* access memory space to the Athena's SDRAM.
*
* Note that OATRAN applies only to memory accesses, not
* to I/O accesses.
*
* To program OATRAN to make Athena virtual address space
* and PCI address space have the same values, OATRAN
* is to be programmed to 0xB8000000. The top seven
* bits of the value mimic the seven bits clipped off
* by the PCI Host controller.
*
* With OATRAN at the said value, when the CPU does
* an access to its virtual address at, say 0xB900_5000,
* the address appearing on the PCI bus will be
* 0xB900_5000.
* - Michael Penner
*/
#define MSP_PCI_OATRAN 0xB8000000UL
#define MSP_PCI_SPACE_BASE (MSP_PCI_OATRAN + 0x1002000UL)
#define MSP_PCI_SPACE_SIZE (0x3000000UL - 0x2000)
#define MSP_PCI_SPACE_END \
(MSP_PCI_SPACE_BASE + MSP_PCI_SPACE_SIZE - 1)
#define MSP_PCI_IOSPACE_BASE (MSP_PCI_OATRAN + 0x1001000UL)
#define MSP_PCI_IOSPACE_SIZE 0x1000
#define MSP_PCI_IOSPACE_END \
(MSP_PCI_IOSPACE_BASE + MSP_PCI_IOSPACE_SIZE - 1)
/* IRQ for PCI status interrupts */
#define PCI_STAT_IRQ 20
#define QFLUSH_REG_1 0xB7F40000
typedef volatile unsigned int pcireg;
typedef void * volatile ppcireg;
struct pci_block_copy
{
pcireg unused1; /* +0x00 */
pcireg unused2; /* +0x04 */
ppcireg unused3; /* +0x08 */
ppcireg unused4; /* +0x0C */
pcireg unused5; /* +0x10 */
pcireg unused6; /* +0x14 */
pcireg unused7; /* +0x18 */
ppcireg unused8; /* +0x1C */
ppcireg unused9; /* +0x20 */
pcireg unusedA; /* +0x24 */
ppcireg unusedB; /* +0x28 */
ppcireg unusedC; /* +0x2C */
};
enum
{
config_device_vendor, /* 0 */
config_status_command, /* 1 */
config_class_revision, /* 2 */
config_BIST_header_latency_cache, /* 3 */
config_BAR0, /* 4 */
config_BAR1, /* 5 */
config_BAR2, /* 6 */
config_not_used7, /* 7 */
config_not_used8, /* 8 */
config_not_used9, /* 9 */
config_CIS, /* 10 */
config_subsystem, /* 11 */
config_not_used12, /* 12 */
config_capabilities, /* 13 */
config_not_used14, /* 14 */
config_lat_grant_irq, /* 15 */
config_message_control,/* 16 */
config_message_addr, /* 17 */
config_message_data, /* 18 */
config_VPD_addr, /* 19 */
config_VPD_data, /* 20 */
config_maxregs /* 21 - number of registers */
};
struct msp_pci_regs
{
pcireg hop_unused_00; /* +0x00 */
pcireg hop_unused_04; /* +0x04 */
pcireg hop_unused_08; /* +0x08 */
pcireg hop_unused_0C; /* +0x0C */
pcireg hop_unused_10; /* +0x10 */
pcireg hop_unused_14; /* +0x14 */
pcireg hop_unused_18; /* +0x18 */
pcireg hop_unused_1C; /* +0x1C */
pcireg hop_unused_20; /* +0x20 */
pcireg hop_unused_24; /* +0x24 */
pcireg hop_unused_28; /* +0x28 */
pcireg hop_unused_2C; /* +0x2C */
pcireg hop_unused_30; /* +0x30 */
pcireg hop_unused_34; /* +0x34 */
pcireg if_control; /* +0x38 */
pcireg oatran; /* +0x3C */
pcireg reset_ctl; /* +0x40 */
pcireg config_addr; /* +0x44 */
pcireg hop_unused_48; /* +0x48 */
pcireg msg_signaled_int_status; /* +0x4C */
pcireg msg_signaled_int_mask; /* +0x50 */
pcireg if_status; /* +0x54 */
pcireg if_mask; /* +0x58 */
pcireg hop_unused_5C; /* +0x5C */
pcireg hop_unused_60; /* +0x60 */
pcireg hop_unused_64; /* +0x64 */
pcireg hop_unused_68; /* +0x68 */
pcireg hop_unused_6C; /* +0x6C */
pcireg hop_unused_70; /* +0x70 */
struct pci_block_copy pci_bc[2] __attribute__((aligned(64)));
pcireg error_hdr1; /* +0xE0 */
pcireg error_hdr2; /* +0xE4 */
pcireg config[config_maxregs] __attribute__((aligned(256)));
};
#define BPCI_CFGADDR_BUSNUM_SHF 16
#define BPCI_CFGADDR_FUNCTNUM_SHF 8
#define BPCI_CFGADDR_REGNUM_SHF 2
#define BPCI_CFGADDR_ENABLE (1<<31)
#define BPCI_IFCONTROL_RTO (1<<20) /* Retry timeout */
#define BPCI_IFCONTROL_HCE (1<<16) /* Host configuration enable */
#define BPCI_IFCONTROL_CTO_SHF 12 /* Shift count for CTO bits */
#define BPCI_IFCONTROL_SE (1<<5) /* Enable exceptions on errors */
#define BPCI_IFCONTROL_BIST (1<<4) /* Use BIST in per. mode */
#define BPCI_IFCONTROL_CAP (1<<3) /* Enable capabilities */
#define BPCI_IFCONTROL_MMC_SHF 0 /* Shift count for MMC bits */
#define BPCI_IFSTATUS_MGT (1<<8) /* Master Grant timeout */
#define BPCI_IFSTATUS_MTT (1<<9) /* Master TRDY timeout */
#define BPCI_IFSTATUS_MRT (1<<10) /* Master retry timeout */
#define BPCI_IFSTATUS_BC0F (1<<13) /* Block copy 0 fault */
#define BPCI_IFSTATUS_BC1F (1<<14) /* Block copy 1 fault */
#define BPCI_IFSTATUS_PCIU (1<<15) /* PCI unable to respond */
#define BPCI_IFSTATUS_BSIZ (1<<16) /* PCI access with illegal size */
#define BPCI_IFSTATUS_BADD (1<<17) /* PCI access with illegal addr */
#define BPCI_IFSTATUS_RTO (1<<18) /* Retry time out */
#define BPCI_IFSTATUS_SER (1<<19) /* System error */
#define BPCI_IFSTATUS_PER (1<<20) /* Parity error */
#define BPCI_IFSTATUS_LCA (1<<21) /* Local CPU abort */
#define BPCI_IFSTATUS_MEM (1<<22) /* Memory prot. violation */
#define BPCI_IFSTATUS_ARB (1<<23) /* Arbiter timed out */
#define BPCI_IFSTATUS_STA (1<<27) /* Signaled target abort */
#define BPCI_IFSTATUS_TA (1<<28) /* Target abort */
#define BPCI_IFSTATUS_MA (1<<29) /* Master abort */
#define BPCI_IFSTATUS_PEI (1<<30) /* Parity error as initiator */
#define BPCI_IFSTATUS_PET (1<<31) /* Parity error as target */
#define BPCI_RESETCTL_PR (1<<0) /* True if reset asserted */
#define BPCI_RESETCTL_RT (1<<4) /* Release time */
#define BPCI_RESETCTL_CT (1<<8) /* Config time */
#define BPCI_RESETCTL_PE (1<<12) /* PCI enabled */
#define BPCI_RESETCTL_HM (1<<13) /* PCI host mode */
#define BPCI_RESETCTL_RI (1<<14) /* PCI reset in */
extern struct msp_pci_regs msp_pci_regs
__attribute__((section(".register")));
extern unsigned long msp_pci_config_space
__attribute__((section(".register")));
#endif /* !_MSP_PCI_H_ */
arch/mips/include/asm/mach-pmcs-msp71xx/msp_prom.h deleted 100644 → 0
View file @ 10760dde
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* MIPS boards bootprom interface for the Linux kernel.
*
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
* Author: Carsten Langgaard, carstenl@mips.com
*
* ########################################################################
*
* ########################################################################
*/
#ifndef _ASM_MSP_PROM_H
#define _ASM_MSP_PROM_H
#include <linux/types.h>
#define DEVICEID "deviceid"
#define FEATURES "features"
#define PROM_ENV "prom_env"
#define PROM_ENV_FILE "/proc/"PROM_ENV
#define PROM_ENV_SIZE 256
#define CPU_DEVID_FAMILY 0x0000ff00
#define CPU_DEVID_REVISION 0x000000ff
#define FPGA_IS_POLO(revision) \
(((revision >= 0xb0) && (revision < 0xd0)))
#define FPGA_IS_5000(revision) \
((revision >= 0x80) && (revision <= 0x90))
#define FPGA_IS_ZEUS(revision) ((revision < 0x7f))
#define FPGA_IS_DUET(revision) \
(((revision >= 0xa0) && (revision < 0xb0)))
#define FPGA_IS_MSP4200(revision) ((revision >= 0xd0))
#define FPGA_IS_MSP7100(revision) ((revision >= 0xd0))
#define MACHINE_TYPE_POLO "POLO"
#define MACHINE_TYPE_DUET "DUET"
#define MACHINE_TYPE_ZEUS "ZEUS"
#define MACHINE_TYPE_MSP2000REVB "MSP2000REVB"
#define MACHINE_TYPE_MSP5000 "MSP5000"
#define MACHINE_TYPE_MSP4200 "MSP4200"
#define MACHINE_TYPE_MSP7120 "MSP7120"
#define MACHINE_TYPE_MSP7130 "MSP7130"
#define MACHINE_TYPE_OTHER "OTHER"
#define MACHINE_TYPE_POLO_FPGA "POLO-FPGA"
#define MACHINE_TYPE_DUET_FPGA "DUET-FPGA"
#define MACHINE_TYPE_ZEUS_FPGA "ZEUS_FPGA"
#define MACHINE_TYPE_MSP2000REVB_FPGA "MSP2000REVB-FPGA"
#define MACHINE_TYPE_MSP5000_FPGA "MSP5000-FPGA"
#define MACHINE_TYPE_MSP4200_FPGA "MSP4200-FPGA"
#define MACHINE_TYPE_MSP7100_FPGA "MSP7100-FPGA"
#define MACHINE_TYPE_OTHER_FPGA "OTHER-FPGA"
/* Device Family definitions */
#define FAMILY_FPGA 0x0000
#define FAMILY_ZEUS 0x1000
#define FAMILY_POLO 0x2000
#define FAMILY_DUET 0x4000
#define FAMILY_TRIAD 0x5000
#define FAMILY_MSP4200 0x4200
#define FAMILY_MSP4200_FPGA 0x4f00
#define FAMILY_MSP7100 0x7100
#define FAMILY_MSP7100_FPGA 0x7f00
/* Device Type definitions */
#define TYPE_MSP7120 0x7120
#define TYPE_MSP7130 0x7130
#define ENET_KEY 'E'
#define ENETTXD_KEY 'e'
#define PCI_KEY 'P'
#define PCIMUX_KEY 'p'
#define SEC_KEY 'S'
#define SPAD_KEY 'D'
#define TDM_KEY 'T'
#define ZSP_KEY 'Z'
#define FEATURE_NOEXIST '-'
#define FEATURE_EXIST '+'
#define ENET_MII 'M'
#define ENET_RMII 'R'
#define ENETTXD_FALLING 'F'
#define ENETTXD_RISING 'R'
#define PCI_HOST 'H'
#define PCI_PERIPHERAL 'P'
#define PCIMUX_FULL 'F'
#define PCIMUX_SINGLE 'S'
#define SEC_DUET 'D'
#define SEC_POLO 'P'
#define SEC_SLOW 'S'
#define SEC_TRIAD 'T'
#define SPAD_POLO 'P'
#define TDM_DUET 'D' /* DUET TDMs might exist */
#define TDM_POLO 'P' /* POLO TDMs might exist */
#define TDM_TRIAD 'T' /* TRIAD TDMs might exist */
#define ZSP_DUET 'D' /* one DUET zsp engine */
#define ZSP_TRIAD 'T' /* two TRIAD zsp engines */
extern char *prom_getenv(char *name);
extern void prom_init_cmdline(void);
extern void prom_meminit(void);
extern void prom_fixup_mem_map(unsigned long start_mem,
unsigned long end_mem);
extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr);
extern unsigned long get_deviceid(void);
extern char identify_enet(unsigned long interface_num);
extern char identify_enetTxD(unsigned long interface_num);
extern char identify_pci(void);
extern char identify_sec(void);
extern char identify_spad(void);
extern char identify_sec(void);
extern char identify_tdm(void);
extern char identify_zsp(void);
extern unsigned long identify_family(void);
extern unsigned long identify_revision(void);
/*
* The following macro calls prom_printf and puts the format string
* into an init section so it can be reclaimed.
*/
#define ppfinit(f, x...) \
do { \
static char _f[] __initdata = KERN_INFO f; \
printk(_f, ## x); \
} while (0)
/* Memory descriptor management. */
#define PROM_MAX_PMEMBLOCKS 7 /* 6 used */
enum yamon_memtypes {
yamon_dontuse,
yamon_prom,
yamon_free,
};
struct prom_pmemblock {
unsigned long base; /* Within KSEG0. */
unsigned int size; /* In bytes. */
unsigned int type; /* free or prom memory */
};
extern int prom_argc;
extern char **prom_argv;
extern char **prom_envp;
extern int *prom_vec;
extern struct prom_pmemblock *prom_getmdesc(void);
#endif /* !_ASM_MSP_PROM_H */
arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h deleted 100644 → 0
View file @ 10760dde
/*
* SMP/VPE-safe functions to access "registers" (see note).
*
* NOTES:
* - These macros use ll/sc instructions, so it is your responsibility to
* ensure these are available on your platform before including this file.
* - The MIPS32 spec states that ll/sc results are undefined for uncached
* accesses. This means they can't be used on HW registers accessed
* through kseg1. Code which requires these macros for this purpose must
* front-end the registers with cached memory "registers" and have a single
* thread update the actual HW registers.
* - A maximum of 2k of code can be inserted between ll and sc. Every
* memory accesses between the instructions will increase the chance of
* sc failing and having to loop.
* - When using custom_read_reg32/custom_write_reg32 only perform the
* necessary logical operations on the register value in between these
* two calls. All other logic should be performed before the first call.
* - There is a bug on the R10000 chips which has a workaround. If you
* are affected by this bug, make sure to define the symbol 'R10000_LLSC_WAR'
* to be non-zero. If you are using this header from within linux, you may
* include <asm/war.h> before including this file to have this defined
* appropriately for you.
*
* Copyright 2005-2007 PMC-Sierra, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc., 675
* Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_REGOPS_H__
#define __ASM_REGOPS_H__
#include <linux/types.h>
#include <asm/compiler.h>
#include <asm/war.h>
#ifndef R10000_LLSC_WAR
#define R10000_LLSC_WAR 0
#endif
#if R10000_LLSC_WAR == 1
#define __beqz "beqzl "
#else
#define __beqz "beqz "
#endif
#ifndef _LINUX_TYPES_H
typedef unsigned int u32;
#endif
/*
* Sets all the masked bits to the corresponding value bits
*/
static inline void set_value_reg32(volatile u32 *const addr,
u32 const mask,
u32 const value)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set arch=r4000 \n"
"1: ll %0, %1 # set_value_reg32 \n"
" and %0, %2 \n"
" or %0, %3 \n"
" sc %0, %1 \n"
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
: "ir" (~mask), "ir" (value), GCC_OFF_SMALL_ASM() (*addr));
}
/*
* Sets all the masked bits to '1'
*/
static inline void set_reg32(volatile u32 *const addr,
u32 const mask)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set arch=r4000 \n"
"1: ll %0, %1 # set_reg32 \n"
" or %0, %2 \n"
" sc %0, %1 \n"
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
: "ir" (mask), GCC_OFF_SMALL_ASM() (*addr));
}
/*
* Sets all the masked bits to '0'
*/
static inline void clear_reg32(volatile u32 *const addr,
u32 const mask)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set arch=r4000 \n"
"1: ll %0, %1 # clear_reg32 \n"
" and %0, %2 \n"
" sc %0, %1 \n"
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
: "ir" (~mask), GCC_OFF_SMALL_ASM() (*addr));
}
/*
* Toggles all masked bits from '0' to '1' and '1' to '0'
*/
static inline void toggle_reg32(volatile u32 *const addr,
u32 const mask)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set arch=r4000 \n"
"1: ll %0, %1 # toggle_reg32 \n"
" xor %0, %2 \n"
" sc %0, %1 \n"
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
: "ir" (mask), GCC_OFF_SMALL_ASM() (*addr));
}
/*
* Read all masked bits others are returned as '0'
*/
static inline u32 read_reg32(volatile u32 *const addr,
u32 const mask)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set noreorder \n"
" lw %0, %1 # read \n"
" and %0, %2 # mask \n"
" .set pop \n"
: "=&r" (temp)
: "m" (*addr), "ir" (mask));
return temp;
}
/*
* blocking_read_reg32 - Read address with blocking load
*
* Uncached writes need to be read back to ensure they reach RAM.
* The returned value must be 'used' to prevent from becoming a
* non-blocking load.
*/
static inline u32 blocking_read_reg32(volatile u32 *const addr)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set noreorder \n"
" lw %0, %1 # read \n"
" move %0, %0 # block \n"
" .set pop \n"
: "=&r" (temp)
: "m" (*addr));
return temp;
}
/*
* For special strange cases only:
*
* If you need custom processing within a ll/sc loop, use the following macros
* VERY CAREFULLY:
*
* u32 tmp; <-- Define a variable to hold the data
*
* custom_read_reg32(address, tmp); <-- Reads the address and put the value
* in the 'tmp' variable given
*
* From here on out, you are (basically) atomic, so don't do anything too
* fancy!
* Also, this code may loop if the end of this block fails to write
* everything back safely due do the other CPU, so do NOT do anything
* with side-effects!
*
* custom_write_reg32(address, tmp); <-- Writes back 'tmp' safely.
*/
#define custom_read_reg32(address, tmp) \
__asm__ __volatile__( \
" .set push \n" \
" .set arch=r4000 \n" \
"1: ll %0, %1 #custom_read_reg32 \n" \
" .set pop \n" \
: "=r" (tmp), "=" GCC_OFF_SMALL_ASM() (*address) \
: GCC_OFF_SMALL_ASM() (*address))
#define custom_write_reg32(address, tmp) \
__asm__ __volatile__( \
" .set push \n" \
" .set arch=r4000 \n" \
" sc %0, %1 #custom_write_reg32 \n" \
" "__beqz"%0, 1b \n" \
" nop \n" \
" .set pop \n" \
: "=&r" (tmp), "=" GCC_OFF_SMALL_ASM() (*address) \
: "0" (tmp), GCC_OFF_SMALL_ASM() (*address))
#endif /* __ASM_REGOPS_H__ */
arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h deleted 100644 → 0
View file @ 10760dde
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arch/mips/include/asm/mach-pmcs-msp71xx/msp_slp_int.h deleted 100644 → 0
View file @ 10760dde
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Defines for the MSP interrupt controller.
*
* Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
* Author: Carsten Langgaard, carstenl@mips.com
*
* ########################################################################
*
* ########################################################################
*/
#ifndef _MSP_SLP_INT_H
#define _MSP_SLP_INT_H
/*
* The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
* hierarchical system. The first level are the direct MIPS interrupts
* and are assigned the interrupt range 0-7. The second level is the SLM
* interrupt controller and is assigned the range 8-39. The third level
* comprises the Peripherial block, the PCI block, the PCI MSI block and
* the SLP. The PCI interrupts and the SLP errors are handled by the
* relevant subsystems so the core interrupt code needs only concern
* itself with the Peripheral block. These are assigned interrupts in
* the range 40-71.
*/
/*
* IRQs directly connected to CPU
*/
#define MSP_MIPS_INTBASE 0
#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
#define MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */
#define MSP_INT_VE 5 /* IRQ for Voice Engine, C_IRQ3 */
#define MSP_INT_SLP 6 /* IRQ for SLM block, C_IRQ4 */
#define MSP_INT_TIMER 7 /* IRQ for the MIPS timer, C_IRQ5 */
/*
* IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
* These defines should be tied to the register definition for the SLM
* interrupt routine. For now, just use hard-coded values.
*/
#define MSP_SLP_INTBASE (MSP_MIPS_INTBASE + 8)
#define MSP_INT_EXT0 (MSP_SLP_INTBASE + 0)
/* External interrupt 0 */
#define MSP_INT_EXT1 (MSP_SLP_INTBASE + 1)
/* External interrupt 1 */
#define MSP_INT_EXT2 (MSP_SLP_INTBASE + 2)
/* External interrupt 2 */
#define MSP_INT_EXT3 (MSP_SLP_INTBASE + 3)
/* External interrupt 3 */
/* Reserved 4-7 */
/*
*************************************************************************
* DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *
* Some MSP produces have this interrupt labelled as Voice and some are *
* SEC mbox ... *
*************************************************************************
*/
#define MSP_INT_SLP_VE (MSP_SLP_INTBASE + 8)
/* Cascaded IRQ for Voice Engine*/
#define MSP_INT_SLP_TDM (MSP_SLP_INTBASE + 9)
/* TDM interrupt */
#define MSP_INT_SLP_MAC0 (MSP_SLP_INTBASE + 10)
/* Cascaded IRQ for MAC 0 */
#define MSP_INT_SLP_MAC1 (MSP_SLP_INTBASE + 11)
/* Cascaded IRQ for MAC 1 */
#define MSP_INT_SEC (MSP_SLP_INTBASE + 12)
/* IRQ for security engine */
#define MSP_INT_PER (MSP_SLP_INTBASE + 13)
/* Peripheral interrupt */
#define MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14)
/* SLP timer 0 */
#define MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15)
/* SLP timer 1 */
#define MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16)
/* SLP timer 2 */
#define MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17)
/* Cascaded MIPS timer */
#define MSP_INT_BLKCP (MSP_SLP_INTBASE + 18)
/* Block Copy */
#define MSP_INT_UART0 (MSP_SLP_INTBASE + 19)
/* UART 0 */
#define MSP_INT_PCI (MSP_SLP_INTBASE + 20)
/* PCI subsystem */
#define MSP_INT_PCI_DBELL (MSP_SLP_INTBASE + 21)
/* PCI doorbell */
#define MSP_INT_PCI_MSI (MSP_SLP_INTBASE + 22)
/* PCI Message Signal */
#define MSP_INT_PCI_BC0 (MSP_SLP_INTBASE + 23)
/* PCI Block Copy 0 */
#define MSP_INT_PCI_BC1 (MSP_SLP_INTBASE + 24)
/* PCI Block Copy 1 */
#define MSP_INT_SLP_ERR (MSP_SLP_INTBASE + 25)
/* SLP error condition */
#define MSP_INT_MAC2 (MSP_SLP_INTBASE + 26)
/* IRQ for MAC2 */
/* Reserved 26-31 */
/*
* IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
*/
#define MSP_PER_INTBASE (MSP_SLP_INTBASE + 32)
/* Reserved 0-1 */
#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
/* UART 1 */
/* Reserved 3-5 */
#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
/* 2-wire */
#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
/* Peripheral timer block out 0 */
#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
/* Peripheral timer block out 1 */
/* Reserved 9 */
#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
/* SPI RX complete */
#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
/* SPI TX complete */
#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
/* GPIO */
#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
/* Peripheral error */
/* Reserved 14-31 */
#endif /* !_MSP_SLP_INT_H */
arch/mips/include/asm/mach-pmcs-msp71xx/msp_usb.h deleted 100644 → 0
View file @ 10760dde
/* SPDX-License-Identifier: GPL-2.0-or-later */
/******************************************************************
* Copyright (c) 2000-2007 PMC-Sierra INC.
*
* PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
* SOFTWARE.
*/
#ifndef MSP_USB_H_
#define MSP_USB_H_
#define NUM_USB_DEVS 1
/* Register spaces for USB host 0 */
#define MSP_USB0_MAB_START (MSP_USB0_BASE + 0x0)
#define MSP_USB0_MAB_END (MSP_USB0_BASE + 0x17)
#define MSP_USB0_ID_START (MSP_USB0_BASE + 0x40000)
#define MSP_USB0_ID_END (MSP_USB0_BASE + 0x4008f)
#define MSP_USB0_HS_START (MSP_USB0_BASE + 0x40100)
#define MSP_USB0_HS_END (MSP_USB0_BASE + 0x401FF)
/* Register spaces for USB host 1 */
#define MSP_USB1_MAB_START (MSP_USB1_BASE + 0x0)
#define MSP_USB1_MAB_END (MSP_USB1_BASE + 0x17)
#define MSP_USB1_ID_START (MSP_USB1_BASE + 0x40000)
#define MSP_USB1_ID_END (MSP_USB1_BASE + 0x4008f)
#define MSP_USB1_HS_START (MSP_USB1_BASE + 0x40100)
#define MSP_USB1_HS_END (MSP_USB1_BASE + 0x401ff)
/* USB Identification registers */
struct msp_usbid_regs {
u32 id; /* 0x0: Identification register */
u32 hwgen; /* 0x4: General HW params */
u32 hwhost; /* 0x8: Host HW params */
u32 hwdev; /* 0xc: Device HW params */
u32 hwtxbuf; /* 0x10: Tx buffer HW params */
u32 hwrxbuf; /* 0x14: Rx buffer HW params */
u32 reserved[26];
u32 timer0_load; /* 0x80: General-purpose timer 0 load*/
u32 timer0_ctrl; /* 0x84: General-purpose timer 0 control */
u32 timer1_load; /* 0x88: General-purpose timer 1 load*/
u32 timer1_ctrl; /* 0x8c: General-purpose timer 1 control */
};
/* MSBus to AMBA registers */
struct msp_mab_regs {
u32 isr; /* 0x0: Interrupt status */
u32 imr; /* 0x4: Interrupt mask */
u32 thcr0; /* 0x8: Transaction header capture 0 */
u32 thcr1; /* 0xc: Transaction header capture 1 */
u32 int_stat; /* 0x10: Interrupt status summary */
u32 phy_cfg; /* 0x14: USB phy config */
};
/* EHCI registers */
struct msp_usbhs_regs {
u32 hciver; /* 0x0: Version and offset to operational regs */
u32 hcsparams; /* 0x4: Host control structural parameters */
u32 hccparams; /* 0x8: Host control capability parameters */
u32 reserved0[5];
u32 dciver; /* 0x20: Device interface version */
u32 dccparams; /* 0x24: Device control capability parameters */
u32 reserved1[6];
u32 cmd; /* 0x40: USB command */
u32 sts; /* 0x44: USB status */
u32 int_ena; /* 0x48: USB interrupt enable */
u32 frindex; /* 0x4c: Frame index */
u32 reserved3;
union {
struct {
u32 flb_addr; /* 0x54: Frame list base address */
u32 next_async_addr; /* 0x58: next asynchronous addr */
u32 ttctrl; /* 0x5c: embedded transaction translator
async buffer status */
u32 burst_size; /* 0x60: Controller burst size */
u32 tx_fifo_ctrl; /* 0x64: Tx latency FIFO tuning */
u32 reserved0[4];
u32 endpt_nak; /* 0x78: Endpoint NAK */
u32 endpt_nak_ena; /* 0x7c: Endpoint NAK enable */
u32 cfg_flag; /* 0x80: Config flag */
u32 port_sc1; /* 0x84: Port status & control 1 */
u32 reserved1[7];
u32 otgsc; /* 0xa4: OTG status & control */
u32 mode; /* 0xa8: USB controller mode */
} host;
struct {
u32 dev_addr; /* 0x54: Device address */
u32 endpt_list_addr; /* 0x58: Endpoint list address */
u32 reserved0[7];
u32 endpt_nak; /* 0x74 */
u32 endpt_nak_ctrl; /* 0x78 */
u32 cfg_flag; /* 0x80 */
u32 port_sc1; /* 0x84: Port status & control 1 */
u32 reserved[7];
u32 otgsc; /* 0xa4: OTG status & control */
u32 mode; /* 0xa8: USB controller mode */
u32 endpt_setup_stat; /* 0xac */
u32 endpt_prime; /* 0xb0 */
u32 endpt_flush; /* 0xb4 */
u32 endpt_stat; /* 0xb8 */
u32 endpt_complete; /* 0xbc */
u32 endpt_ctrl0; /* 0xc0 */
u32 endpt_ctrl1; /* 0xc4 */
u32 endpt_ctrl2; /* 0xc8 */
u32 endpt_ctrl3; /* 0xcc */
} device;
} u;
};
/*
* Container for the more-generic platform_device.
* This exists mainly as a way to map the non-standard register
* spaces and make them accessible to the USB ISR.
*/
struct mspusb_device {
struct msp_mab_regs __iomem *mab_regs;
struct msp_usbid_regs __iomem *usbid_regs;
struct msp_usbhs_regs __iomem *usbhs_regs;
struct platform_device dev;
};
#define to_mspusb_device(x) container_of((x), struct mspusb_device, dev)
#define TO_HOST_ID(x) ((x) & 0x3)
#endif /*MSP_USB_H_*/
arch/mips/include/asm/mach-pmcs-msp71xx/war.h deleted 100644 → 0
View file @ 10760dde
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_PMC_SIERRA_WAR_H
#define __ASM_MIPS_PMC_SIERRA_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
defined(CONFIG_PMC_MSP7120_FPGA)
#define MIPS34K_MISSED_ITLB_WAR 1
#else
#define MIPS34K_MISSED_ITLB_WAR 0
#endif
#endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */
arch/mips/pci/Makefile
View file @ 1b00767f
......@@ -35,9 +35,6 @@ obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
obj-$(CONFIG_MACH_LOONGSON64) += fixup-loongson3.o ops-loongson3.o
obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o pci-malta.o
obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o
obj-$(CONFIG_SGI_IP27) += pci-ip27.o
obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o
obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
......
arch/mips/pci/fixup-pmcmsp.c deleted 100644 → 0
View file @ 10760dde
/*
* PMC-Sierra MSP board specific pci fixups.
*
* Copyright 2001 MontaVista Software Inc.
* Copyright 2005-2007 PMC-Sierra, Inc
*
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifdef CONFIG_PCI
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/byteorder.h>
#include <msp_pci.h>
#include <msp_cic_int.h>
/* PCI interrupt pins */
#define IRQ4 MSP_INT_EXT4
#define IRQ5 MSP_INT_EXT5
#define IRQ6 MSP_INT_EXT6
#if defined(CONFIG_PMC_MSP7120_GW)
/* Garibaldi Board IRQ wiring to PCI slots */
static char irq_tab[][5] = {
/* INTA INTB INTC INTD */
{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
{0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
{0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
{0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
{0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
{0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
{0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
{0, 0, 0, 0, 0 }, /* 6 (AD[16]): Unused */
{0, 0, 0, 0, 0 }, /* 7 (AD[17]): Unused */
{0, 0, 0, 0, 0 }, /* 8 (AD[18]): Unused */
{0, 0, 0, 0, 0 }, /* 9 (AD[19]): Unused */
{0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
{0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
{0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
{0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
{0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
{0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
{0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
{0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
{0, IRQ4, IRQ4, 0, 0 }, /* 18 (AD[28]): slot 0 */
{0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
{0, IRQ5, IRQ5, 0, 0 }, /* 20 (AD[30]): slot 1 */
{0, IRQ6, IRQ6, 0, 0 } /* 21 (AD[31]): slot 2 */
};
#elif defined(CONFIG_PMC_MSP7120_EVAL)
/* MSP7120 Eval Board IRQ wiring to PCI slots */
static char irq_tab[][5] = {
/* INTA INTB INTC INTD */
{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
{0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
{0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
{0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
{0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
{0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
{0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
{0, IRQ6, IRQ6, 0, 0 }, /* 6 (AD[16]): slot 3 (mini) */
{0, IRQ5, IRQ5, 0, 0 }, /* 7 (AD[17]): slot 2 (mini) */
{0, IRQ4, IRQ4, IRQ4, IRQ4}, /* 8 (AD[18]): slot 0 (PCI) */
{0, IRQ5, IRQ5, IRQ5, IRQ5}, /* 9 (AD[19]): slot 1 (PCI) */
{0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
{0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
{0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
{0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
{0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
{0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
{0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
{0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
{0, 0, 0, 0, 0 }, /* 18 (AD[28]): Unused */
{0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
{0, 0, 0, 0, 0 }, /* 20 (AD[30]): Unused */
{0, 0, 0, 0, 0 } /* 21 (AD[31]): Unused */
};
#else
/* Unknown board -- don't assign any IRQs */
static char irq_tab[][5] = {
/* INTA INTB INTC INTD */
{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
{0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
{0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
{0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
{0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
{0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
{0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
{0, 0, 0, 0, 0 }, /* 6 (AD[16]): Unused */
{0, 0, 0, 0, 0 }, /* 7 (AD[17]): Unused */
{0, 0, 0, 0, 0 }, /* 8 (AD[18]): Unused */
{0, 0, 0, 0, 0 }, /* 9 (AD[19]): Unused */
{0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
{0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
{0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
{0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
{0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
{0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
{0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
{0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
{0, 0, 0, 0, 0 }, /* 18 (AD[28]): Unused */
{0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
{0, 0, 0, 0, 0 }, /* 20 (AD[30]): Unused */
{0, 0, 0, 0, 0 } /* 21 (AD[31]): Unused */
};
#endif
/*****************************************************************************
*
* FUNCTION: pcibios_plat_dev_init
* _________________________________________________________________________
*
* DESCRIPTION: Perform platform specific device initialization at
* pci_enable_device() time.
* None are needed for the MSP7120 PCI Controller.
*
* INPUTS: dev - structure describing the PCI device
*
* OUTPUTS: none
*
* RETURNS: PCIBIOS_SUCCESSFUL
*
****************************************************************************/
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return PCIBIOS_SUCCESSFUL;
}
/*****************************************************************************
*
* FUNCTION: pcibios_map_irq
* _________________________________________________________________________
*
* DESCRIPTION: Perform board supplied PCI IRQ mapping routine.
*
* INPUTS: dev - unused
* slot - PCI slot. Identified by which bit of the AD[] bus
* drives the IDSEL line. AD[10] is 0, AD[31] is
* slot 21.
* pin - numbered using the scheme of the PCI_INTERRUPT_PIN
* field of the config header.
*
* OUTPUTS: none
*
* RETURNS: IRQ number
*
****************************************************************************/
int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
#if !defined(CONFIG_PMC_MSP7120_GW) && !defined(CONFIG_PMC_MSP7120_EVAL)
printk(KERN_WARNING "PCI: unknown board, no PCI IRQs assigned.\n");
#endif
printk(KERN_WARNING "PCI: irq_tab returned %d for slot=%d pin=%d\n",
irq_tab[slot][pin], slot, pin);
return irq_tab[slot][pin];
}
#endif /* CONFIG_PCI */
arch/mips/pci/ops-pmcmsp.c deleted 100644 → 0
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arch/mips/pmcs-msp71xx/Kconfig deleted 100644 → 0
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# SPDX-License-Identifier: GPL-2.0
choice
prompt "PMC-Sierra MSP SOC type"
depends on PMC_MSP
config PMC_MSP4200_EVAL
bool "PMC-Sierra MSP4200 Eval Board"
select IRQ_MSP_SLP
select HAVE_PCI
select MIPS_L1_CACHE_SHIFT_4
config PMC_MSP4200_GW
bool "PMC-Sierra MSP4200 VoIP Gateway"
select IRQ_MSP_SLP
select HAVE_PCI
config PMC_MSP7120_EVAL
bool "PMC-Sierra MSP7120 Eval Board"
select SYS_SUPPORTS_MULTITHREADING
select IRQ_MSP_CIC
select HAVE_PCI
config PMC_MSP7120_GW
bool "PMC-Sierra MSP7120 Residential Gateway"
select SYS_SUPPORTS_MULTITHREADING
select IRQ_MSP_CIC
select HAVE_PCI
select MSP_HAS_USB
select MSP_ETH
config PMC_MSP7120_FPGA
bool "PMC-Sierra MSP7120 FPGA"
select SYS_SUPPORTS_MULTITHREADING
select IRQ_MSP_CIC
select HAVE_PCI
endchoice
config MSP_HAS_USB
bool
depends on PMC_MSP
config MSP_ETH
bool
select MSP_HAS_MAC
depends on PMC_MSP
config MSP_HAS_MAC
bool
depends on PMC_MSP
arch/mips/pmcs-msp71xx/Makefile deleted 100644 → 0
View file @ 10760dde
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for the PMC-Sierra MSP SOCs
#
obj-y += msp_prom.o msp_setup.o msp_irq.o \
msp_time.o msp_serial.o msp_elb.o
obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o
obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o
obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o msp_irq_per.o
obj-$(CONFIG_PCI) += msp_pci.o
obj-$(CONFIG_MSP_HAS_MAC) += msp_eth.o
obj-$(CONFIG_MSP_HAS_USB) += msp_usb.o
obj-$(CONFIG_MIPS_MT_SMP) += msp_smp.o
arch/mips/pmcs-msp71xx/Platform deleted 100644 → 0
View file @ 10760dde
#
# PMC-Sierra MSP SOCs
#
platform-$(CONFIG_PMC_MSP) += pmcs-msp71xx/
cflags-$(CONFIG_PMC_MSP) += -I$(srctree)/arch/mips/include/asm/mach-pmcs-msp71xx \
-mno-branch-likely
load-$(CONFIG_PMC_MSP) += 0xffffffff80100000
arch/mips/pmcs-msp71xx/msp_elb.c deleted 100644 → 0
View file @ 10760dde
/*
* Sets up the proper Chip Select configuration registers. It is assumed that
* PMON sets up the ADDR and MASK registers properly.
*
* Copyright 2005-2006 PMC-Sierra, Inc.
* Author: Marc St-Jean, Marc_St-Jean@pmc-sierra.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <msp_regs.h>
static int __init msp_elb_setup(void)
{
#if defined(CONFIG_PMC_MSP7120_GW) \
|| defined(CONFIG_PMC_MSP7120_EVAL)
/*
* Force all CNFG to be identical and equal to CS0,
* according to OPS doc
*/
*CS1_CNFG_REG = *CS2_CNFG_REG = *CS3_CNFG_REG = *CS0_CNFG_REG;
#endif
return 0;
}
subsys_initcall(msp_elb_setup);
arch/mips/pmcs-msp71xx/msp_eth.c deleted 100644 → 0
View file @ 10760dde
/*
* The setup file for ethernet related hardware on PMC-Sierra MSP processors.
*
* Copyright 2010 PMC-Sierra, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <msp_regs.h>
#include <msp_int.h>
#include <msp_gpio_macros.h>
#define MSP_ETHERNET_GPIO0 14
#define MSP_ETHERNET_GPIO1 15
#define MSP_ETHERNET_GPIO2 16
#define MSP_ETH_ID "pmc_mspeth"
#define MSP_ETH_SIZE 0xE0
static struct resource msp_eth0_resources[] = {
[0] = {
.start = MSP_MAC0_BASE,
.end = MSP_MAC0_BASE + MSP_ETH_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MSP_INT_MAC0,
.end = MSP_INT_MAC0,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msp_eth1_resources[] = {
[0] = {
.start = MSP_MAC1_BASE,
.end = MSP_MAC1_BASE + MSP_ETH_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MSP_INT_MAC1,
.end = MSP_INT_MAC1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mspeth_device[] = {
[0] = {
.name = MSP_ETH_ID,
.id = 0,
.num_resources = ARRAY_SIZE(msp_eth0_resources),
.resource = msp_eth0_resources,
},
[1] = {
.name = MSP_ETH_ID,
.id = 1,
.num_resources = ARRAY_SIZE(msp_eth1_resources),
.resource = msp_eth1_resources,
},
};
#define msp_eth_devs mspeth_device
int __init msp_eth_setup(void)
{
int i, ret = 0;
/* Configure the GPIO and take the ethernet PHY out of reset */
msp_gpio_pin_mode(MSP_GPIO_OUTPUT, MSP_ETHERNET_GPIO0);
msp_gpio_pin_hi(MSP_ETHERNET_GPIO0);
for (i = 0; i < ARRAY_SIZE(msp_eth_devs); i++) {
ret = platform_device_register(&msp_eth_devs[i]);
printk(KERN_INFO "device: %d, return value = %d\n", i, ret);
if (ret) {
platform_device_unregister(&msp_eth_devs[i]);
break;
}
}
if (ret)
printk(KERN_WARNING "Could not initialize "
"MSPETH device structures.\n");
return ret;
}
subsys_initcall(msp_eth_setup);
arch/mips/pmcs-msp71xx/msp_hwbutton.c deleted 100644 → 0
View file @ 10760dde
/*
* Sets up interrupt handlers for various hardware switches which are
* connected to interrupt lines.
*
* Copyright 2005-2207 PMC-Sierra, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <msp_int.h>
#include <msp_regs.h>
#include <msp_regops.h>
/* For hwbutton_interrupt->initial_state */
#define HWBUTTON_HI 0x1
#define HWBUTTON_LO 0x2
/*
* This struct describes a hardware button
*/
struct hwbutton_interrupt {
char *name; /* Name of button */
int irq; /* Actual LINUX IRQ */
int eirq; /* Extended IRQ number (0-7) */
int initial_state; /* The "normal" state of the switch */
void (*handle_hi)(void *); /* Handler: switch input has gone HI */
void (*handle_lo)(void *); /* Handler: switch input has gone LO */
void *data; /* Optional data to pass to handler */
};
#ifdef CONFIG_PMC_MSP7120_GW
extern void msp_restart(char *);
static void softreset_push(void *data)
{
printk(KERN_WARNING "SOFTRESET switch was pushed\n");
/*
* In the future you could move this to the release handler,
* timing the difference between the 'push' and 'release', and only
* doing this ungraceful restart if the button has been down for
* a certain amount of time; otherwise doing a graceful restart.
*/
msp_restart(NULL);
}
static void softreset_release(void *data)
{
printk(KERN_WARNING "SOFTRESET switch was released\n");
/* Do nothing */
}
static void standby_on(void *data)
{
printk(KERN_WARNING "STANDBY switch was set to ON (not implemented)\n");
/* TODO: Put board in standby mode */
}
static void standby_off(void *data)
{
printk(KERN_WARNING
"STANDBY switch was set to OFF (not implemented)\n");
/* TODO: Take out of standby mode */
}
static struct hwbutton_interrupt softreset_sw = {
.name = "Softreset button",
.irq = MSP_INT_EXT0,
.eirq = 0,
.initial_state = HWBUTTON_HI,
.handle_hi = softreset_release,
.handle_lo = softreset_push,
.data = NULL,
};
static struct hwbutton_interrupt standby_sw = {
.name = "Standby switch",
.irq = MSP_INT_EXT1,
.eirq = 1,
.initial_state = HWBUTTON_HI,
.handle_hi = standby_off,
.handle_lo = standby_on,
.data = NULL,
};
#endif /* CONFIG_PMC_MSP7120_GW */
static irqreturn_t hwbutton_handler(int irq, void *data)
{
struct hwbutton_interrupt *hirq = data;
unsigned long cic_ext = *CIC_EXT_CFG_REG;
if (CIC_EXT_IS_ACTIVE_HI(cic_ext, hirq->eirq)) {
/* Interrupt: pin is now HI */
CIC_EXT_SET_ACTIVE_LO(cic_ext, hirq->eirq);
hirq->handle_hi(hirq->data);
} else {
/* Interrupt: pin is now LO */
CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq);
hirq->handle_lo(hirq->data);
}
/*
* Invert the POLARITY of this level interrupt to ack the interrupt
* Thus next state change will invoke the opposite message
*/
*CIC_EXT_CFG_REG = cic_ext;
return IRQ_HANDLED;
}
static int msp_hwbutton_register(struct hwbutton_interrupt *hirq)
{
unsigned long cic_ext;
if (hirq->handle_hi == NULL || hirq->handle_lo == NULL)
return -EINVAL;
cic_ext = *CIC_EXT_CFG_REG;
CIC_EXT_SET_TRIGGER_LEVEL(cic_ext, hirq->eirq);
if (hirq->initial_state == HWBUTTON_HI)
CIC_EXT_SET_ACTIVE_LO(cic_ext, hirq->eirq);
else
CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq);
*CIC_EXT_CFG_REG = cic_ext;
return request_irq(hirq->irq, hwbutton_handler, 0,
hirq->name, hirq);
}
static int __init msp_hwbutton_setup(void)
{
#ifdef CONFIG_PMC_MSP7120_GW
msp_hwbutton_register(&softreset_sw);
msp_hwbutton_register(&standby_sw);
#endif
return 0;
}
subsys_initcall(msp_hwbutton_setup);
arch/mips/pmcs-msp71xx/msp_irq.c deleted 100644 → 0
View file @ 10760dde
/*
* IRQ vector handles
*
* Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/ptrace.h>
#include <linux/time.h>
#include <asm/irq_cpu.h>
#include <asm/setup.h>
#include <msp_int.h>
/* SLP bases systems */
extern void msp_slp_irq_init(void);
extern void msp_slp_irq_dispatch(void);
/* CIC based systems */
extern void msp_cic_irq_init(void);
extern void msp_cic_irq_dispatch(void);
/* VSMP support init */
extern void msp_vsmp_int_init(void);
/* vectored interrupt implementation */
/* SW0/1 interrupts are used for SMP */
static inline void mac0_int_dispatch(void) { do_IRQ(MSP_INT_MAC0); }
static inline void mac1_int_dispatch(void) { do_IRQ(MSP_INT_MAC1); }
static inline void mac2_int_dispatch(void) { do_IRQ(MSP_INT_SAR); }
static inline void usb_int_dispatch(void) { do_IRQ(MSP_INT_USB); }
static inline void sec_int_dispatch(void) { do_IRQ(MSP_INT_SEC); }
/*
* The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded
* hierarchical system. The first level are the direct MIPS interrupts
* and are assigned the interrupt range 0-7. The second level is the SLM
* interrupt controller and is assigned the range 8-39. The third level
* comprises the Peripherial block, the PCI block, the PCI MSI block and
* the SLP. The PCI interrupts and the SLP errors are handled by the
* relevant subsystems so the core interrupt code needs only concern
* itself with the Peripheral block. These are assigned interrupts in
* the range 40-71.
*/
asmlinkage void plat_irq_dispatch(void)
{
u32 pending;
pending = read_c0_status() & read_c0_cause();
/*
* jump to the correct interrupt routine
* These are arranged in priority order and the timer
* comes first!
*/
#ifdef CONFIG_IRQ_MSP_CIC /* break out the CIC stuff for now */
if (pending & C_IRQ4) /* do the peripherals first, that's the timer */
msp_cic_irq_dispatch();
else if (pending & C_IRQ0)
do_IRQ(MSP_INT_MAC0);
else if (pending & C_IRQ1)
do_IRQ(MSP_INT_MAC1);
else if (pending & C_IRQ2)
do_IRQ(MSP_INT_USB);
else if (pending & C_IRQ3)
do_IRQ(MSP_INT_SAR);
else if (pending & C_IRQ5)
do_IRQ(MSP_INT_SEC);
#else
if (pending & C_IRQ5)
do_IRQ(MSP_INT_TIMER);
else if (pending & C_IRQ0)
do_IRQ(MSP_INT_MAC0);
else if (pending & C_IRQ1)
do_IRQ(MSP_INT_MAC1);
else if (pending & C_IRQ3)
do_IRQ(MSP_INT_VE);
else if (pending & C_IRQ4)
msp_slp_irq_dispatch();
#endif
else if (pending & C_SW0) /* do software after hardware */
do_IRQ(MSP_INT_SW0);
else if (pending & C_SW1)
do_IRQ(MSP_INT_SW1);
}
void __init arch_init_irq(void)
{
/* assume we'll be using vectored interrupt mode except in UP mode*/
#ifdef CONFIG_MIPS_MT
BUG_ON(!cpu_has_vint);
#endif
/* initialize the 1st-level CPU based interrupt controller */
mips_cpu_irq_init();
#ifdef CONFIG_IRQ_MSP_CIC
msp_cic_irq_init();
#ifdef CONFIG_MIPS_MT
set_vi_handler(MSP_INT_CIC, msp_cic_irq_dispatch);
set_vi_handler(MSP_INT_MAC0, mac0_int_dispatch);
set_vi_handler(MSP_INT_MAC1, mac1_int_dispatch);
set_vi_handler(MSP_INT_SAR, mac2_int_dispatch);
set_vi_handler(MSP_INT_USB, usb_int_dispatch);
set_vi_handler(MSP_INT_SEC, sec_int_dispatch);
#ifdef CONFIG_MIPS_MT_SMP
msp_vsmp_int_init();
#endif /* CONFIG_MIPS_MT_SMP */
#endif /* CONFIG_MIPS_MT */
/* setup the cascaded interrupts */
if (request_irq(MSP_INT_CIC, no_action, IRQF_NO_THREAD,
"MSP CIC cascade", NULL))
pr_err("Failed to register MSP CIC cascade interrupt\n");
if (request_irq(MSP_INT_PER, no_action, IRQF_NO_THREAD,
"MSP PER cascade", NULL))
pr_err("Failed to register MSP PER cascade interrupt\n");
#else
/*
* Setup the 2nd-level SLP register based interrupt controller.
* VSMP support support is not enabled for SLP.
*/
msp_slp_irq_init();
/* setup the cascaded SLP/PER interrupts */
if (request_irq(MSP_INT_SLP, no_action, IRQF_NO_THREAD,
"MSP CIC cascade", NULL))
pr_err("Failed to register MSP CIC cascade interrupt\n");
if (request_irq(MSP_INT_PER, no_action, IRQF_NO_THREAD,
"MSP PER cascade", NULL))
pr_err("Failed to register MSP PER cascade interrupt\n");
#endif
}
arch/mips/pmcs-msp71xx/msp_irq_cic.c deleted 100644 → 0
View file @ 10760dde
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2010 PMC-Sierra, Inc, derived from irq_cpu.c
*
* This file define the irq handler for MSP CIC subsystem interrupts.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <asm/mipsregs.h>
#include <msp_cic_int.h>
#include <msp_regs.h>
/*
* External API
*/
extern void msp_per_irq_init(void);
extern void msp_per_irq_dispatch(void);
/*
* Convenience Macro. Should be somewhere generic.
*/
#define get_current_vpe() \
((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE)
#ifdef CONFIG_SMP
#define LOCK_VPE(flags, mtflags) \
do { \
local_irq_save(flags); \
mtflags = dmt(); \
} while (0)
#define UNLOCK_VPE(flags, mtflags) \
do { \
emt(mtflags); \
local_irq_restore(flags);\
} while (0)
#define LOCK_CORE(flags, mtflags) \
do { \
local_irq_save(flags); \
mtflags = dvpe(); \
} while (0)
#define UNLOCK_CORE(flags, mtflags) \
do { \
evpe(mtflags); \
local_irq_restore(flags);\
} while (0)
#else
#define LOCK_VPE(flags, mtflags)
#define UNLOCK_VPE(flags, mtflags)
#endif
/* ensure writes to cic are completed */
static inline void cic_wmb(void)
{
const volatile void __iomem *cic_mem = CIC_VPE0_MSK_REG;
volatile u32 dummy_read;
wmb();
dummy_read = __raw_readl(cic_mem);
dummy_read++;
}
static void unmask_cic_irq(struct irq_data *d)
{
volatile u32 *cic_msk_reg = CIC_VPE0_MSK_REG;
int vpe;
#ifdef CONFIG_SMP
unsigned int mtflags;
unsigned long flags;
/*
* Make sure we have IRQ affinity. It may have changed while
* we were processing the IRQ.
*/
if (!cpumask_test_cpu(smp_processor_id(),
irq_data_get_affinity_mask(d)))
return;
#endif
vpe = get_current_vpe();
LOCK_VPE(flags, mtflags);
cic_msk_reg[vpe] |= (1 << (d->irq - MSP_CIC_INTBASE));
UNLOCK_VPE(flags, mtflags);
cic_wmb();
}
static void mask_cic_irq(struct irq_data *d)
{
volatile u32 *cic_msk_reg = CIC_VPE0_MSK_REG;
int vpe = get_current_vpe();
#ifdef CONFIG_SMP
unsigned long flags, mtflags;
#endif
LOCK_VPE(flags, mtflags);
cic_msk_reg[vpe] &= ~(1 << (d->irq - MSP_CIC_INTBASE));
UNLOCK_VPE(flags, mtflags);
cic_wmb();
}
static void msp_cic_irq_ack(struct irq_data *d)
{
mask_cic_irq(d);
/*
* Only really necessary for 18, 16-14 and sometimes 3:0
* (since these can be edge sensitive) but it doesn't
* hurt for the others
*/
*CIC_STS_REG = (1 << (d->irq - MSP_CIC_INTBASE));
}
/* Note: Limiting to VSMP. */
#ifdef CONFIG_MIPS_MT_SMP
static int msp_cic_irq_set_affinity(struct irq_data *d,
const struct cpumask *cpumask, bool force)
{
int cpu;
unsigned long flags;
unsigned int mtflags;
unsigned long imask = (1 << (d->irq - MSP_CIC_INTBASE));
volatile u32 *cic_mask = (volatile u32 *)CIC_VPE0_MSK_REG;
/* timer balancing should be disabled in kernel code */
BUG_ON(d->irq == MSP_INT_VPE0_TIMER || d->irq == MSP_INT_VPE1_TIMER);
LOCK_CORE(flags, mtflags);
/* enable if any of each VPE's TCs require this IRQ */
for_each_online_cpu(cpu) {
if (cpumask_test_cpu(cpu, cpumask))
cic_mask[cpu] |= imask;
else
cic_mask[cpu] &= ~imask;
}
UNLOCK_CORE(flags, mtflags);
return 0;
}
#endif
static struct irq_chip msp_cic_irq_controller = {
.name = "MSP_CIC",
.irq_mask = mask_cic_irq,
.irq_mask_ack = msp_cic_irq_ack,
.irq_unmask = unmask_cic_irq,
.irq_ack = msp_cic_irq_ack,
#ifdef CONFIG_MIPS_MT_SMP
.irq_set_affinity = msp_cic_irq_set_affinity,
#endif
};
void __init msp_cic_irq_init(void)
{
int i;
/* Mask/clear interrupts. */
*CIC_VPE0_MSK_REG = 0x00000000;
*CIC_VPE1_MSK_REG = 0x00000000;
*CIC_STS_REG = 0xFFFFFFFF;
/*
* The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI.
* These inputs map to EXT_INT_POL[6:4] inside the CIC.
* They are to be active low, level sensitive.
*/
*CIC_EXT_CFG_REG &= 0xFFFF8F8F;
/* initialize all the IRQ descriptors */
for (i = MSP_CIC_INTBASE ; i < MSP_CIC_INTBASE + 32 ; i++) {
irq_set_chip_and_handler(i, &msp_cic_irq_controller,
handle_level_irq);
}
/* Initialize the PER interrupt sub-system */
msp_per_irq_init();
}
/* CIC masked by CIC vector processing before dispatch called */
void msp_cic_irq_dispatch(void)
{
volatile u32 *cic_msk_reg = (volatile u32 *)CIC_VPE0_MSK_REG;
u32 cic_mask;
u32 pending;
int cic_status = *CIC_STS_REG;
cic_mask = cic_msk_reg[get_current_vpe()];
pending = cic_status & cic_mask;
if (pending & (1 << (MSP_INT_VPE0_TIMER - MSP_CIC_INTBASE))) {
do_IRQ(MSP_INT_VPE0_TIMER);
} else if (pending & (1 << (MSP_INT_VPE1_TIMER - MSP_CIC_INTBASE))) {
do_IRQ(MSP_INT_VPE1_TIMER);
} else if (pending & (1 << (MSP_INT_PER - MSP_CIC_INTBASE))) {
msp_per_irq_dispatch();
} else if (pending) {
do_IRQ(ffs(pending) + MSP_CIC_INTBASE - 1);
} else{
spurious_interrupt();
}
}
arch/mips/pmcs-msp71xx/msp_irq_per.c deleted 100644 → 0
View file @ 10760dde
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2010 PMC-Sierra, Inc, derived from irq_cpu.c
*
* This file define the irq handler for MSP PER subsystem interrupts.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/bitops.h>
#include <asm/mipsregs.h>
#include <msp_cic_int.h>
#include <msp_regs.h>
/*
* Convenience Macro. Should be somewhere generic.
*/
#define get_current_vpe() \
((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE)
#ifdef CONFIG_SMP
/*
* The PER registers must be protected from concurrent access.
*/
static DEFINE_SPINLOCK(per_lock);
#endif
/* ensure writes to per are completed */
static inline void per_wmb(void)
{
const volatile void __iomem *per_mem = PER_INT_MSK_REG;
volatile u32 dummy_read;
wmb();
dummy_read = __raw_readl(per_mem);
dummy_read++;
}
static inline void unmask_per_irq(struct irq_data *d)
{
#ifdef CONFIG_SMP
unsigned long flags;
spin_lock_irqsave(&per_lock, flags);
*PER_INT_MSK_REG |= (1 << (d->irq - MSP_PER_INTBASE));
spin_unlock_irqrestore(&per_lock, flags);
#else
*PER_INT_MSK_REG |= (1 << (d->irq - MSP_PER_INTBASE));
#endif
per_wmb();
}
static inline void mask_per_irq(struct irq_data *d)
{
#ifdef CONFIG_SMP
unsigned long flags;
spin_lock_irqsave(&per_lock, flags);
*PER_INT_MSK_REG &= ~(1 << (d->irq - MSP_PER_INTBASE));
spin_unlock_irqrestore(&per_lock, flags);
#else
*PER_INT_MSK_REG &= ~(1 << (d->irq - MSP_PER_INTBASE));
#endif
per_wmb();
}
static inline void msp_per_irq_ack(struct irq_data *d)
{
mask_per_irq(d);
/*
* In the PER interrupt controller, only bits 11 and 10
* are write-to-clear, (SPI TX complete, SPI RX complete).
* It does nothing for any others.
*/
*PER_INT_STS_REG = (1 << (d->irq - MSP_PER_INTBASE));
}
#ifdef CONFIG_SMP
static int msp_per_irq_set_affinity(struct irq_data *d,
const struct cpumask *affinity, bool force)
{
/* WTF is this doing ????? */
unmask_per_irq(d);
return 0;
}
#endif
static struct irq_chip msp_per_irq_controller = {
.name = "MSP_PER",
.irq_enable = unmask_per_irq,
.irq_disable = mask_per_irq,
.irq_ack = msp_per_irq_ack,
#ifdef CONFIG_SMP
.irq_set_affinity = msp_per_irq_set_affinity,
#endif
};
void __init msp_per_irq_init(void)
{
int i;
/* Mask/clear interrupts. */
*PER_INT_MSK_REG = 0x00000000;
*PER_INT_STS_REG = 0xFFFFFFFF;
/* initialize all the IRQ descriptors */
for (i = MSP_PER_INTBASE; i < MSP_PER_INTBASE + 32; i++) {
irq_set_chip(i, &msp_per_irq_controller);
}
}
void msp_per_irq_dispatch(void)
{
u32 per_mask = *PER_INT_MSK_REG;
u32 per_status = *PER_INT_STS_REG;
u32 pending;
pending = per_status & per_mask;
if (pending) {
do_IRQ(ffs(pending) + MSP_PER_INTBASE - 1);
} else {
spurious_interrupt();
}
}
arch/mips/pmcs-msp71xx/msp_irq_slp.c deleted 100644 → 0
View file @ 10760dde
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* This file define the irq handler for MSP SLM subsystem interrupts.
*
* Copyright 2005-2006 PMC-Sierra, Inc, derived from irq_cpu.c
* Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <asm/mipsregs.h>
#include <msp_slp_int.h>
#include <msp_regs.h>
static inline void unmask_msp_slp_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
/* check for PER interrupt range */
if (irq < MSP_PER_INTBASE)
*SLP_INT_MSK_REG |= (1 << (irq - MSP_SLP_INTBASE));
else
*PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE));
}
static inline void mask_msp_slp_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
/* check for PER interrupt range */
if (irq < MSP_PER_INTBASE)
*SLP_INT_MSK_REG &= ~(1 << (irq - MSP_SLP_INTBASE));
else
*PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE));
}
/*
* While we ack the interrupt interrupts are disabled and thus we don't need
* to deal with concurrency issues. Same for msp_slp_irq_end.
*/
static inline void ack_msp_slp_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
/* check for PER interrupt range */
if (irq < MSP_PER_INTBASE)
*SLP_INT_STS_REG = (1 << (irq - MSP_SLP_INTBASE));
else
*PER_INT_STS_REG = (1 << (irq - MSP_PER_INTBASE));
}
static struct irq_chip msp_slp_irq_controller = {
.name = "MSP_SLP",
.irq_ack = ack_msp_slp_irq,
.irq_mask = mask_msp_slp_irq,
.irq_unmask = unmask_msp_slp_irq,
};
void __init msp_slp_irq_init(void)
{
int i;
/* Mask/clear interrupts. */
*SLP_INT_MSK_REG = 0x00000000;
*PER_INT_MSK_REG = 0x00000000;
*SLP_INT_STS_REG = 0xFFFFFFFF;
*PER_INT_STS_REG = 0xFFFFFFFF;
/* initialize all the IRQ descriptors */
for (i = MSP_SLP_INTBASE; i < MSP_PER_INTBASE + 32; i++)
irq_set_chip_and_handler(i, &msp_slp_irq_controller,
handle_level_irq);
}
void msp_slp_irq_dispatch(void)
{
u32 pending;
int intbase;
intbase = MSP_SLP_INTBASE;
pending = *SLP_INT_STS_REG & *SLP_INT_MSK_REG;
/* check for PER interrupt */
if (pending == (1 << (MSP_INT_PER - MSP_SLP_INTBASE))) {
intbase = MSP_PER_INTBASE;
pending = *PER_INT_STS_REG & *PER_INT_MSK_REG;
}
/* check for spurious interrupt */
if (pending == 0x00000000) {
printk(KERN_ERR "Spurious %s interrupt?\n",
(intbase == MSP_SLP_INTBASE) ? "SLP" : "PER");
return;
}
/* dispatch the irq */
do_IRQ(ffs(pending) + intbase - 1);
}
arch/mips/pmcs-msp71xx/msp_pci.c deleted 100644 → 0
View file @ 10760dde
/*
* The setup file for PCI related hardware on PMC-Sierra MSP processors.
*
* Copyright 2005-2006 PMC-Sierra, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <msp_prom.h>
#include <msp_regs.h>
extern void msp_pci_init(void);
static int __init msp_pci_setup(void)
{
#if 0 /* Linux 2.6 initialization code to be completed */
if (getdeviceid() & DEV_ID_SINGLE_PC) {
/* If single card mode */
slmRegs *sreg = (slmRegs *) SREG_BASE;
sreg->single_pc_enable = SINGLE_PCCARD;
}
#endif
msp_pci_init();
return 0;
}
subsys_initcall(msp_pci_setup);
arch/mips/pmcs-msp71xx/msp_prom.c deleted 100644 → 0
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arch/mips/pmcs-msp71xx/msp_serial.c deleted 100644 → 0
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arch/mips/pmcs-msp71xx/msp_setup.c deleted 100644 → 0
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arch/mips/pmcs-msp71xx/msp_smp.c deleted 100644 → 0
View file @ 10760dde
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
* Copyright (C) 2001 Ralf Baechle
* Copyright (C) 2010 PMC-Sierra, Inc.
*
* VSMP support for MSP platforms . Derived from malta vsmp support.
*/
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <asm/setup.h>
#ifdef CONFIG_MIPS_MT_SMP
#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for call */
static void ipi_resched_dispatch(void)
{
do_IRQ(MIPS_CPU_IPI_RESCHED_IRQ);
}
static void ipi_call_dispatch(void)
{
do_IRQ(MIPS_CPU_IPI_CALL_IRQ);
}
static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
{
return IRQ_HANDLED;
}
static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
{
generic_smp_call_function_interrupt();
return IRQ_HANDLED;
}
void __init arch_init_ipiirq(int irq, const char *name, irq_handler_t handler)
{
if (request_irq(irq, handler, IRQF_PERCPU, name, NULL))
pr_err("Failed to request irq %d (%s)\n", irq, name);
irq_set_handler(irq, handle_percpu_irq);
}
void __init msp_vsmp_int_init(void)
{
set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
arch_init_ipiirq(MIPS_CPU_IPI_RESCHED_IRQ, "IPI_resched",
ipi_resched_interrupt);
arch_init_ipiirq(MIPS_CPU_IPI_CALL_IRQ, "IPI_call", ipi_call_interrupt);
}
#endif /* CONFIG_MIPS_MT_SMP */
arch/mips/pmcs-msp71xx/msp_time.c deleted 100644 → 0
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arch/mips/pmcs-msp71xx/msp_usb.c deleted 100644 → 0
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