Commit 1bcbba30 authored by David Howells's avatar David Howells Committed by Linus Torvalds

[PATCH] FRV: Use the generic IRQ stuff

Make the FRV arch use the generic IRQ code rather than having its own
routines for doing so.
Signed-off-by: default avatarDavid Howells <dhowells@redhat.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 8d6b5eee
......@@ -27,7 +27,7 @@ config GENERIC_CALIBRATE_DELAY
config GENERIC_HARDIRQS
bool
default n
default y
config GENERIC_TIME
bool
......@@ -251,6 +251,12 @@ config MB93091_NO_MB
endchoice
endif
config FUJITSU_MB93493
bool "MB93493 Multimedia chip"
help
Select this option if the MB93493 multimedia chip is going to be
used.
choice
prompt "GP-Relative data support"
default GPREL_DATA_8
......
......@@ -10,15 +10,14 @@ extra-y:= head.o init_task.o vmlinux.lds
obj-y := $(heads-y) entry.o entry-table.o break.o switch_to.o kernel_thread.o \
process.o traps.o ptrace.o signal.o dma.o \
sys_frv.o time.o semaphore.o setup.o frv_ksyms.o \
debug-stub.o irq.o irq-routing.o sleep.o uaccess.o
debug-stub.o irq.o sleep.o uaccess.o
obj-$(CONFIG_GDBSTUB) += gdb-stub.o gdb-io.o
obj-$(CONFIG_MB93091_VDK) += irq-mb93091.o
obj-$(CONFIG_MB93093_PDK) += irq-mb93093.o
obj-$(CONFIG_FUJITSU_MB93493) += irq-mb93493.o
obj-$(CONFIG_PM) += pm.o cmode.o
obj-$(CONFIG_MB93093_PDK) += pm-mb93093.o
obj-$(CONFIG_FUJITSU_MB93493) += irq-mb93493.o
obj-$(CONFIG_SYSCTL) += sysctl.o
obj-$(CONFIG_FUTEX) += futex.o
obj-$(CONFIG_MODULES) += module.o
......@@ -24,7 +24,6 @@
#include <asm/delay.h>
#include <asm/irq.h>
#include <asm/irc-regs.h>
#include <asm/irq-routing.h>
#define __reg16(ADDR) (*(volatile unsigned short *)(ADDR))
......@@ -33,83 +32,129 @@
#define __get_IFR() ({ __reg16(0xffc0000c); })
#define __clr_IFR(M) do { __reg16(0xffc0000c) = ~(M); wmb(); } while(0)
static void frv_fpga_doirq(struct irq_source *source);
static void frv_fpga_control(struct irq_group *group, int irq, int on);
/*****************************************************************************/
/*
* FPGA IRQ multiplexor
* on-motherboard FPGA PIC operations
*/
static struct irq_source frv_fpga[4] = {
#define __FPGA(X, M) \
[X] = { \
.muxname = "fpga."#X, \
.irqmask = M, \
.doirq = frv_fpga_doirq, \
}
static void frv_fpga_enable(unsigned int irq)
{
uint16_t imr = __get_IMR();
__FPGA(0, 0x0028),
__FPGA(1, 0x0050),
__FPGA(2, 0x1c00),
__FPGA(3, 0x6386),
};
static struct irq_group frv_fpga_irqs = {
.first_irq = IRQ_BASE_FPGA,
.control = frv_fpga_control,
.sources = {
[ 1] = &frv_fpga[3],
[ 2] = &frv_fpga[3],
[ 3] = &frv_fpga[0],
[ 4] = &frv_fpga[1],
[ 5] = &frv_fpga[0],
[ 6] = &frv_fpga[1],
[ 7] = &frv_fpga[3],
[ 8] = &frv_fpga[3],
[ 9] = &frv_fpga[3],
[10] = &frv_fpga[2],
[11] = &frv_fpga[2],
[12] = &frv_fpga[2],
[13] = &frv_fpga[3],
[14] = &frv_fpga[3],
},
};
imr &= ~(1 << (irq - IRQ_BASE_FPGA));
__set_IMR(imr);
}
static void frv_fpga_control(struct irq_group *group, int index, int on)
static void frv_fpga_disable(unsigned int irq)
{
uint16_t imr = __get_IMR();
if (on)
imr &= ~(1 << index);
else
imr |= 1 << index;
imr |= 1 << (irq - IRQ_BASE_FPGA);
__set_IMR(imr);
}
static void frv_fpga_doirq(struct irq_source *source)
static void frv_fpga_ack(unsigned int irq)
{
__clr_IFR(1 << (irq - IRQ_BASE_FPGA));
}
static void frv_fpga_end(unsigned int irq)
{
}
static struct irq_chip frv_fpga_pic = {
.name = "mb93091",
.enable = frv_fpga_enable,
.disable = frv_fpga_disable,
.ack = frv_fpga_ack,
.mask = frv_fpga_disable,
.unmask = frv_fpga_enable,
.end = frv_fpga_end,
};
/*
* FPGA PIC interrupt handler
*/
static irqreturn_t fpga_interrupt(int irq, void *_mask, struct pt_regs *regs)
{
uint16_t mask, imr;
uint16_t imr, mask = (unsigned long) _mask;
irqreturn_t iret = 0;
imr = __get_IMR();
mask = source->irqmask & ~imr & __get_IFR();
if (mask) {
__set_IMR(imr | mask);
__clr_IFR(mask);
distribute_irqs(&frv_fpga_irqs, mask);
__set_IMR(imr);
mask = mask & ~imr & __get_IFR();
/* poll all the triggered IRQs */
while (mask) {
int irq;
asm("scan %1,gr0,%0" : "=r"(irq) : "r"(mask));
irq = 31 - irq;
mask &= ~(1 << irq);
if (__do_IRQ(IRQ_BASE_FPGA + irq, regs))
iret |= IRQ_HANDLED;
}
return iret;
}
/*
* define an interrupt action for each FPGA PIC output
* - use dev_id to indicate the FPGA PIC input to output mappings
*/
static struct irqaction fpga_irq[4] = {
[0] = {
.handler = fpga_interrupt,
.flags = IRQF_DISABLED | IRQF_SHARED,
.mask = CPU_MASK_NONE,
.name = "fpga.0",
.dev_id = (void *) 0x0028UL,
},
[1] = {
.handler = fpga_interrupt,
.flags = IRQF_DISABLED | IRQF_SHARED,
.mask = CPU_MASK_NONE,
.name = "fpga.1",
.dev_id = (void *) 0x0050UL,
},
[2] = {
.handler = fpga_interrupt,
.flags = IRQF_DISABLED | IRQF_SHARED,
.mask = CPU_MASK_NONE,
.name = "fpga.2",
.dev_id = (void *) 0x1c00UL,
},
[3] = {
.handler = fpga_interrupt,
.flags = IRQF_DISABLED | IRQF_SHARED,
.mask = CPU_MASK_NONE,
.name = "fpga.3",
.dev_id = (void *) 0x6386UL,
}
};
/*
* initialise the motherboard FPGA's PIC
*/
void __init fpga_init(void)
{
int irq;
/* all PIC inputs are all set to be low-level driven, apart from the
* NMI button (15) which is fixed at falling-edge
*/
__set_IMR(0x7ffe);
__clr_IFR(0x0000);
frv_irq_route_external(&frv_fpga[0], IRQ_CPU_EXTERNAL0);
frv_irq_route_external(&frv_fpga[1], IRQ_CPU_EXTERNAL1);
frv_irq_route_external(&frv_fpga[2], IRQ_CPU_EXTERNAL2);
frv_irq_route_external(&frv_fpga[3], IRQ_CPU_EXTERNAL3);
frv_irq_set_group(&frv_fpga_irqs);
for (irq = IRQ_BASE_FPGA + 1; irq <= IRQ_BASE_FPGA + 14; irq++)
set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq);
set_irq_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq);
/* the FPGA drives the first four external IRQ inputs on the CPU PIC */
setup_irq(IRQ_CPU_EXTERNAL0, &fpga_irq[0]);
setup_irq(IRQ_CPU_EXTERNAL1, &fpga_irq[1]);
setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[2]);
setup_irq(IRQ_CPU_EXTERNAL3, &fpga_irq[3]);
}
/* irq-mb93093.c: MB93093 FPGA interrupt handling
*
* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
* Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
......@@ -24,7 +24,6 @@
#include <asm/delay.h>
#include <asm/irq.h>
#include <asm/irc-regs.h>
#include <asm/irq-routing.h>
#define __reg16(ADDR) (*(volatile unsigned short *)(__region_CS2 + (ADDR)))
......@@ -33,66 +32,100 @@
#define __get_IFR() ({ __reg16(0x02); })
#define __clr_IFR(M) do { __reg16(0x02) = ~(M); wmb(); } while(0)
static void frv_fpga_doirq(struct irq_source *source);
static void frv_fpga_control(struct irq_group *group, int irq, int on);
/*****************************************************************************/
/*
* FPGA IRQ multiplexor
* off-CPU FPGA PIC operations
*/
static struct irq_source frv_fpga[4] = {
#define __FPGA(X, M) \
[X] = { \
.muxname = "fpga."#X, \
.irqmask = M, \
.doirq = frv_fpga_doirq, \
}
__FPGA(0, 0x0700),
};
static void frv_fpga_enable(unsigned int irq)
{
uint16_t imr = __get_IMR();
static struct irq_group frv_fpga_irqs = {
.first_irq = IRQ_BASE_FPGA,
.control = frv_fpga_control,
.sources = {
[ 8] = &frv_fpga[0],
[ 9] = &frv_fpga[0],
[10] = &frv_fpga[0],
},
};
imr &= ~(1 << (irq - IRQ_BASE_FPGA));
__set_IMR(imr);
}
static void frv_fpga_control(struct irq_group *group, int index, int on)
static void frv_fpga_disable(unsigned int irq)
{
uint16_t imr = __get_IMR();
if (on)
imr &= ~(1 << index);
else
imr |= 1 << index;
imr |= 1 << (irq - IRQ_BASE_FPGA);
__set_IMR(imr);
}
static void frv_fpga_doirq(struct irq_source *source)
static void frv_fpga_ack(unsigned int irq)
{
__clr_IFR(1 << (irq - IRQ_BASE_FPGA));
}
static void frv_fpga_end(unsigned int irq)
{
}
static struct irq_chip frv_fpga_pic = {
.name = "mb93093",
.enable = frv_fpga_enable,
.disable = frv_fpga_disable,
.ack = frv_fpga_ack,
.mask = frv_fpga_disable,
.unmask = frv_fpga_enable,
.end = frv_fpga_end,
};
/*
* FPGA PIC interrupt handler
*/
static irqreturn_t fpga_interrupt(int irq, void *_mask, struct pt_regs *regs)
{
uint16_t mask, imr;
uint16_t imr, mask = (unsigned long) _mask;
irqreturn_t iret = 0;
imr = __get_IMR();
mask = source->irqmask & ~imr & __get_IFR();
if (mask) {
__set_IMR(imr | mask);
__clr_IFR(mask);
distribute_irqs(&frv_fpga_irqs, mask);
__set_IMR(imr);
mask = mask & ~imr & __get_IFR();
/* poll all the triggered IRQs */
while (mask) {
int irq;
asm("scan %1,gr0,%0" : "=r"(irq) : "r"(mask));
irq = 31 - irq;
mask &= ~(1 << irq);
if (__do_IRQ(IRQ_BASE_FPGA + irq, regs))
iret |= IRQ_HANDLED;
}
return iret;
}
/*
* define an interrupt action for each FPGA PIC output
* - use dev_id to indicate the FPGA PIC input to output mappings
*/
static struct irqaction fpga_irq[1] = {
[0] = {
.handler = fpga_interrupt,
.flags = IRQF_DISABLED,
.mask = CPU_MASK_NONE,
.name = "fpga.0",
.dev_id = (void *) 0x0700UL,
}
};
/*
* initialise the motherboard FPGA's PIC
*/
void __init fpga_init(void)
{
int irq;
/* all PIC inputs are all set to be edge triggered */
__set_IMR(0x0700);
__clr_IFR(0x0000);
frv_irq_route_external(&frv_fpga[0], IRQ_CPU_EXTERNAL2);
frv_irq_set_group(&frv_fpga_irqs);
for (irq = IRQ_BASE_FPGA + 8; irq <= IRQ_BASE_FPGA + 10; irq++)
set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq);
/* the FPGA drives external IRQ input #2 on the CPU PIC */
setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[0]);
}
/* irq-mb93493.c: MB93493 companion chip interrupt handler
*
* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
* Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
......@@ -24,84 +24,133 @@
#include <asm/delay.h>
#include <asm/irq.h>
#include <asm/irc-regs.h>
#include <asm/irq-routing.h>
#include <asm/mb93493-irqs.h>
#include <asm/mb93493-regs.h>
static void frv_mb93493_doirq(struct irq_source *source);
#define IRQ_ROUTE_ONE(X) (X##_ROUTE << (X - IRQ_BASE_MB93493))
#define IRQ_ROUTING \
(IRQ_ROUTE_ONE(IRQ_MB93493_VDC) | \
IRQ_ROUTE_ONE(IRQ_MB93493_VCC) | \
IRQ_ROUTE_ONE(IRQ_MB93493_AUDIO_OUT) | \
IRQ_ROUTE_ONE(IRQ_MB93493_I2C_0) | \
IRQ_ROUTE_ONE(IRQ_MB93493_I2C_1) | \
IRQ_ROUTE_ONE(IRQ_MB93493_USB) | \
IRQ_ROUTE_ONE(IRQ_MB93493_LOCAL_BUS) | \
IRQ_ROUTE_ONE(IRQ_MB93493_PCMCIA) | \
IRQ_ROUTE_ONE(IRQ_MB93493_GPIO) | \
IRQ_ROUTE_ONE(IRQ_MB93493_AUDIO_IN))
/*****************************************************************************/
/*
* MB93493 companion chip IRQ multiplexor
* daughter board PIC operations
*/
static struct irq_source frv_mb93493[2] = {
[0] = {
.muxname = "mb93493.0",
.muxdata = __region_CS3 + 0x3d0,
.doirq = frv_mb93493_doirq,
.irqmask = 0x0000,
},
[1] = {
.muxname = "mb93493.1",
.muxdata = __region_CS3 + 0x3d4,
.doirq = frv_mb93493_doirq,
.irqmask = 0x0000,
},
};
static void frv_mb93493_control(struct irq_group *group, int index, int on)
static void frv_mb93493_enable(unsigned int irq)
{
struct irq_source *source;
uint32_t iqsr;
volatile void *piqsr;
if ((frv_mb93493[0].irqmask & (1 << index)))
source = &frv_mb93493[0];
if (IRQ_ROUTING & (1 << (irq - IRQ_BASE_MB93493)))
piqsr = __addr_MB93493_IQSR(1);
else
source = &frv_mb93493[1];
piqsr = __addr_MB93493_IQSR(0);
iqsr = readl(source->muxdata);
if (on)
iqsr |= 1 << (index + 16);
iqsr = readl(piqsr);
iqsr |= 1 << (irq - IRQ_BASE_MB93493 + 16);
writel(iqsr, piqsr);
}
static void frv_mb93493_disable(unsigned int irq)
{
uint32_t iqsr;
volatile void *piqsr;
if (IRQ_ROUTING & (1 << (irq - IRQ_BASE_MB93493)))
piqsr = __addr_MB93493_IQSR(1);
else
iqsr &= ~(1 << (index + 16));
piqsr = __addr_MB93493_IQSR(0);
writel(iqsr, source->muxdata);
iqsr = readl(piqsr);
iqsr &= ~(1 << (irq - IRQ_BASE_MB93493 + 16));
writel(iqsr, piqsr);
}
static struct irq_group frv_mb93493_irqs = {
.first_irq = IRQ_BASE_MB93493,
.control = frv_mb93493_control,
};
static void frv_mb93493_doirq(struct irq_source *source)
static void frv_mb93493_ack(unsigned int irq)
{
uint32_t mask = readl(source->muxdata);
mask = mask & (mask >> 16) & 0xffff;
}
if (mask)
distribute_irqs(&frv_mb93493_irqs, mask);
static void frv_mb93493_end(unsigned int irq)
{
}
static void __init mb93493_irq_route(int irq, int source)
static struct irq_chip frv_mb93493_pic = {
.name = "mb93093",
.enable = frv_mb93493_enable,
.disable = frv_mb93493_disable,
.ack = frv_mb93493_ack,
.mask = frv_mb93493_disable,
.unmask = frv_mb93493_enable,
.end = frv_mb93493_end,
};
/*
* MB93493 PIC interrupt handler
*/
static irqreturn_t mb93493_interrupt(int irq, void *_piqsr, struct pt_regs *regs)
{
frv_mb93493[source].irqmask |= 1 << (irq - IRQ_BASE_MB93493);
frv_mb93493_irqs.sources[irq - IRQ_BASE_MB93493] = &frv_mb93493[source];
volatile void *piqsr = _piqsr;
irqreturn_t iret = 0;
uint32_t iqsr;
iqsr = readl(piqsr);
iqsr = iqsr & (iqsr >> 16) & 0xffff;
/* poll all the triggered IRQs */
while (iqsr) {
int irq;
asm("scan %1,gr0,%0" : "=r"(irq) : "r"(iqsr));
irq = 31 - irq;
iqsr &= ~(1 << irq);
if (__do_IRQ(IRQ_BASE_MB93493 + irq, regs))
iret |= IRQ_HANDLED;
}
return iret;
}
void __init route_mb93493_irqs(void)
/*
* define an interrupt action for each MB93493 PIC output
* - use dev_id to indicate the MB93493 PIC input to output mappings
*/
static struct irqaction mb93493_irq[2] = {
[0] = {
.handler = mb93493_interrupt,
.flags = IRQF_DISABLED | IRQF_SHARED,
.mask = CPU_MASK_NONE,
.name = "mb93493.0",
.dev_id = (void *) __addr_MB93493_IQSR(0),
},
[1] = {
.handler = mb93493_interrupt,
.flags = IRQF_DISABLED | IRQF_SHARED,
.mask = CPU_MASK_NONE,
.name = "mb93493.1",
.dev_id = (void *) __addr_MB93493_IQSR(1),
}
};
/*
* initialise the motherboard MB93493's PIC
*/
void __init mb93493_init(void)
{
frv_irq_route_external(&frv_mb93493[0], IRQ_CPU_MB93493_0);
frv_irq_route_external(&frv_mb93493[1], IRQ_CPU_MB93493_1);
frv_irq_set_group(&frv_mb93493_irqs);
mb93493_irq_route(IRQ_MB93493_VDC, IRQ_MB93493_VDC_ROUTE);
mb93493_irq_route(IRQ_MB93493_VCC, IRQ_MB93493_VCC_ROUTE);
mb93493_irq_route(IRQ_MB93493_AUDIO_IN, IRQ_MB93493_AUDIO_IN_ROUTE);
mb93493_irq_route(IRQ_MB93493_I2C_0, IRQ_MB93493_I2C_0_ROUTE);
mb93493_irq_route(IRQ_MB93493_I2C_1, IRQ_MB93493_I2C_1_ROUTE);
mb93493_irq_route(IRQ_MB93493_USB, IRQ_MB93493_USB_ROUTE);
mb93493_irq_route(IRQ_MB93493_LOCAL_BUS, IRQ_MB93493_LOCAL_BUS_ROUTE);
mb93493_irq_route(IRQ_MB93493_PCMCIA, IRQ_MB93493_PCMCIA_ROUTE);
mb93493_irq_route(IRQ_MB93493_GPIO, IRQ_MB93493_GPIO_ROUTE);
mb93493_irq_route(IRQ_MB93493_AUDIO_OUT, IRQ_MB93493_AUDIO_OUT_ROUTE);
int irq;
for (irq = IRQ_BASE_MB93493 + 0; irq <= IRQ_BASE_MB93493 + 10; irq++)
set_irq_chip_and_handler(irq, &frv_mb93493_pic, handle_edge_irq);
/* the MB93493 drives external IRQ inputs on the CPU PIC */
setup_irq(IRQ_CPU_MB93493_0, &mb93493_irq[0]);
setup_irq(IRQ_CPU_MB93493_1, &mb93493_irq[1]);
}
/* irq-routing.c: IRQ routing
*
* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/sched.h>
#include <linux/random.h>
#include <linux/init.h>
#include <linux/serial_reg.h>
#include <asm/io.h>
#include <asm/irq-routing.h>
#include <asm/irc-regs.h>
#include <asm/serial-regs.h>
#include <asm/dma.h>
struct irq_level frv_irq_levels[16] = {
[0 ... 15] = {
.lock = SPIN_LOCK_UNLOCKED,
}
};
struct irq_group *irq_groups[NR_IRQ_GROUPS];
extern struct irq_group frv_cpu_irqs;
void __init frv_irq_route(struct irq_source *source, int irqlevel)
{
source->level = &frv_irq_levels[irqlevel];
source->next = frv_irq_levels[irqlevel].sources;
frv_irq_levels[irqlevel].sources = source;
}
void __init frv_irq_route_external(struct irq_source *source, int irq)
{
int irqlevel = 0;
switch (irq) {
case IRQ_CPU_EXTERNAL0: irqlevel = IRQ_XIRQ0_LEVEL; break;
case IRQ_CPU_EXTERNAL1: irqlevel = IRQ_XIRQ1_LEVEL; break;
case IRQ_CPU_EXTERNAL2: irqlevel = IRQ_XIRQ2_LEVEL; break;
case IRQ_CPU_EXTERNAL3: irqlevel = IRQ_XIRQ3_LEVEL; break;
case IRQ_CPU_EXTERNAL4: irqlevel = IRQ_XIRQ4_LEVEL; break;
case IRQ_CPU_EXTERNAL5: irqlevel = IRQ_XIRQ5_LEVEL; break;
case IRQ_CPU_EXTERNAL6: irqlevel = IRQ_XIRQ6_LEVEL; break;
case IRQ_CPU_EXTERNAL7: irqlevel = IRQ_XIRQ7_LEVEL; break;
default: BUG();
}
source->level = &frv_irq_levels[irqlevel];
source->next = frv_irq_levels[irqlevel].sources;
frv_irq_levels[irqlevel].sources = source;
}
void __init frv_irq_set_group(struct irq_group *group)
{
irq_groups[group->first_irq >> NR_IRQ_LOG2_ACTIONS_PER_GROUP] = group;
}
void distribute_irqs(struct irq_group *group, unsigned long irqmask)
{
struct irqaction *action;
int irq;
while (irqmask) {
asm("scan %1,gr0,%0" : "=r"(irq) : "r"(irqmask));
if (irq < 0 || irq > 31)
asm volatile("break");
irq = 31 - irq;
irqmask &= ~(1 << irq);
action = group->actions[irq];
irq += group->first_irq;
if (action) {
int status = 0;
// if (!(action->flags & IRQF_DISABLED))
// local_irq_enable();
do {
status |= action->flags;
action->handler(irq, action->dev_id, __frame);
action = action->next;
} while (action);
if (status & IRQF_SAMPLE_RANDOM)
add_interrupt_randomness(irq);
local_irq_disable();
}
}
}
/*****************************************************************************/
/*
* CPU UART interrupts
*/
static void frv_cpuuart_doirq(struct irq_source *source)
{
// uint8_t iir = readb(source->muxdata + UART_IIR * 8);
// if ((iir & 0x0f) != UART_IIR_NO_INT)
distribute_irqs(&frv_cpu_irqs, source->irqmask);
}
struct irq_source frv_cpuuart[2] = {
#define __CPUUART(X, A) \
[X] = { \
.muxname = "uart", \
.muxdata = (volatile void __iomem *)(unsigned long)A,\
.irqmask = 1 << IRQ_CPU_UART##X, \
.doirq = frv_cpuuart_doirq, \
}
__CPUUART(0, UART0_BASE),
__CPUUART(1, UART1_BASE),
};
/*****************************************************************************/
/*
* CPU DMA interrupts
*/
static void frv_cpudma_doirq(struct irq_source *source)
{
uint32_t cstr = readl(source->muxdata + DMAC_CSTRx);
if (cstr & DMAC_CSTRx_INT)
distribute_irqs(&frv_cpu_irqs, source->irqmask);
}
struct irq_source frv_cpudma[8] = {
#define __CPUDMA(X, A) \
[X] = { \
.muxname = "dma", \
.muxdata = (volatile void __iomem *)(unsigned long)A,\
.irqmask = 1 << IRQ_CPU_DMA##X, \
.doirq = frv_cpudma_doirq, \
}
__CPUDMA(0, 0xfe000900),
__CPUDMA(1, 0xfe000980),
__CPUDMA(2, 0xfe000a00),
__CPUDMA(3, 0xfe000a80),
__CPUDMA(4, 0xfe001000),
__CPUDMA(5, 0xfe001080),
__CPUDMA(6, 0xfe001100),
__CPUDMA(7, 0xfe001180),
};
/*****************************************************************************/
/*
* CPU timer interrupts - can't tell whether they've generated an interrupt or not
*/
static void frv_cputimer_doirq(struct irq_source *source)
{
distribute_irqs(&frv_cpu_irqs, source->irqmask);
}
struct irq_source frv_cputimer[3] = {
#define __CPUTIMER(X) \
[X] = { \
.muxname = "timer", \
.muxdata = NULL, \
.irqmask = 1 << IRQ_CPU_TIMER##X, \
.doirq = frv_cputimer_doirq, \
}
__CPUTIMER(0),
__CPUTIMER(1),
__CPUTIMER(2),
};
/*****************************************************************************/
/*
* external CPU interrupts - can't tell directly whether they've generated an interrupt or not
*/
static void frv_cpuexternal_doirq(struct irq_source *source)
{
distribute_irqs(&frv_cpu_irqs, source->irqmask);
}
struct irq_source frv_cpuexternal[8] = {
#define __CPUEXTERNAL(X) \
[X] = { \
.muxname = "ext", \
.muxdata = NULL, \
.irqmask = 1 << IRQ_CPU_EXTERNAL##X, \
.doirq = frv_cpuexternal_doirq, \
}
__CPUEXTERNAL(0),
__CPUEXTERNAL(1),
__CPUEXTERNAL(2),
__CPUEXTERNAL(3),
__CPUEXTERNAL(4),
__CPUEXTERNAL(5),
__CPUEXTERNAL(6),
__CPUEXTERNAL(7),
};
#define set_IRR(N,A,B,C,D) __set_IRR(N, (A << 28) | (B << 24) | (C << 20) | (D << 16))
struct irq_group frv_cpu_irqs = {
.sources = {
[IRQ_CPU_UART0] = &frv_cpuuart[0],
[IRQ_CPU_UART1] = &frv_cpuuart[1],
[IRQ_CPU_TIMER0] = &frv_cputimer[0],
[IRQ_CPU_TIMER1] = &frv_cputimer[1],
[IRQ_CPU_TIMER2] = &frv_cputimer[2],
[IRQ_CPU_DMA0] = &frv_cpudma[0],
[IRQ_CPU_DMA1] = &frv_cpudma[1],
[IRQ_CPU_DMA2] = &frv_cpudma[2],
[IRQ_CPU_DMA3] = &frv_cpudma[3],
[IRQ_CPU_DMA4] = &frv_cpudma[4],
[IRQ_CPU_DMA5] = &frv_cpudma[5],
[IRQ_CPU_DMA6] = &frv_cpudma[6],
[IRQ_CPU_DMA7] = &frv_cpudma[7],
[IRQ_CPU_EXTERNAL0] = &frv_cpuexternal[0],
[IRQ_CPU_EXTERNAL1] = &frv_cpuexternal[1],
[IRQ_CPU_EXTERNAL2] = &frv_cpuexternal[2],
[IRQ_CPU_EXTERNAL3] = &frv_cpuexternal[3],
[IRQ_CPU_EXTERNAL4] = &frv_cpuexternal[4],
[IRQ_CPU_EXTERNAL5] = &frv_cpuexternal[5],
[IRQ_CPU_EXTERNAL6] = &frv_cpuexternal[6],
[IRQ_CPU_EXTERNAL7] = &frv_cpuexternal[7],
},
};
/*****************************************************************************/
/*
* route the CPU's interrupt sources
*/
void __init route_cpu_irqs(void)
{
frv_irq_set_group(&frv_cpu_irqs);
__set_IITMR(0, 0x003f0000); /* DMA0-3, TIMER0-2 IRQ detect levels */
__set_IITMR(1, 0x20000000); /* ERR0-1, UART0-1, DMA4-7 IRQ detect levels */
/* route UART and error interrupts */
frv_irq_route(&frv_cpuuart[0], IRQ_UART0_LEVEL);
frv_irq_route(&frv_cpuuart[1], IRQ_UART1_LEVEL);
set_IRR(6, IRQ_GDBSTUB_LEVEL, IRQ_GDBSTUB_LEVEL, IRQ_UART1_LEVEL, IRQ_UART0_LEVEL);
/* route DMA channel interrupts */
frv_irq_route(&frv_cpudma[0], IRQ_DMA0_LEVEL);
frv_irq_route(&frv_cpudma[1], IRQ_DMA1_LEVEL);
frv_irq_route(&frv_cpudma[2], IRQ_DMA2_LEVEL);
frv_irq_route(&frv_cpudma[3], IRQ_DMA3_LEVEL);
frv_irq_route(&frv_cpudma[4], IRQ_DMA4_LEVEL);
frv_irq_route(&frv_cpudma[5], IRQ_DMA5_LEVEL);
frv_irq_route(&frv_cpudma[6], IRQ_DMA6_LEVEL);
frv_irq_route(&frv_cpudma[7], IRQ_DMA7_LEVEL);
set_IRR(4, IRQ_DMA3_LEVEL, IRQ_DMA2_LEVEL, IRQ_DMA1_LEVEL, IRQ_DMA0_LEVEL);
set_IRR(7, IRQ_DMA7_LEVEL, IRQ_DMA6_LEVEL, IRQ_DMA5_LEVEL, IRQ_DMA4_LEVEL);
/* route timer interrupts */
frv_irq_route(&frv_cputimer[0], IRQ_TIMER0_LEVEL);
frv_irq_route(&frv_cputimer[1], IRQ_TIMER1_LEVEL);
frv_irq_route(&frv_cputimer[2], IRQ_TIMER2_LEVEL);
set_IRR(5, 0, IRQ_TIMER2_LEVEL, IRQ_TIMER1_LEVEL, IRQ_TIMER0_LEVEL);
/* route external interrupts */
frv_irq_route(&frv_cpuexternal[0], IRQ_XIRQ0_LEVEL);
frv_irq_route(&frv_cpuexternal[1], IRQ_XIRQ1_LEVEL);
frv_irq_route(&frv_cpuexternal[2], IRQ_XIRQ2_LEVEL);
frv_irq_route(&frv_cpuexternal[3], IRQ_XIRQ3_LEVEL);
frv_irq_route(&frv_cpuexternal[4], IRQ_XIRQ4_LEVEL);
frv_irq_route(&frv_cpuexternal[5], IRQ_XIRQ5_LEVEL);
frv_irq_route(&frv_cpuexternal[6], IRQ_XIRQ6_LEVEL);
frv_irq_route(&frv_cpuexternal[7], IRQ_XIRQ7_LEVEL);
set_IRR(2, IRQ_XIRQ7_LEVEL, IRQ_XIRQ6_LEVEL, IRQ_XIRQ5_LEVEL, IRQ_XIRQ4_LEVEL);
set_IRR(3, IRQ_XIRQ3_LEVEL, IRQ_XIRQ2_LEVEL, IRQ_XIRQ1_LEVEL, IRQ_XIRQ0_LEVEL);
#if defined(CONFIG_MB93091_VDK)
__set_TM1(0x55550000); /* XIRQ7-0 all active low */
#elif defined(CONFIG_MB93093_PDK)
__set_TM1(0x15550000); /* XIRQ7 active high, 6-0 all active low */
#else
#error dont know external IRQ trigger levels for this setup
#endif
} /* end route_cpu_irqs() */
This diff is collapsed.
......@@ -43,7 +43,6 @@
#include <asm/mb-regs.h>
#include <asm/mb93493-regs.h>
#include <asm/gdb-stub.h>
#include <asm/irq-routing.h>
#include <asm/io.h>
#ifdef CONFIG_BLK_DEV_INITRD
......
......@@ -26,7 +26,6 @@
#include <asm/timer-regs.h>
#include <asm/mb-regs.h>
#include <asm/mb86943a.h>
#include <asm/irq-routing.h>
#include <linux/timex.h>
......
......@@ -15,7 +15,6 @@
#include <asm/io.h>
#include <asm/smp.h>
#include <asm/irq-routing.h>
#include "pci-frv.h"
......
......@@ -14,36 +14,6 @@
#ifndef __ASSEMBLY__
#include <asm/irq-routing.h>
#define IRQ_BASE_CPU (NR_IRQ_ACTIONS_PER_GROUP * 0)
/* IRQ IDs presented to drivers */
enum {
IRQ_CPU__UNUSED = IRQ_BASE_CPU,
IRQ_CPU_UART0,
IRQ_CPU_UART1,
IRQ_CPU_TIMER0,
IRQ_CPU_TIMER1,
IRQ_CPU_TIMER2,
IRQ_CPU_DMA0,
IRQ_CPU_DMA1,
IRQ_CPU_DMA2,
IRQ_CPU_DMA3,
IRQ_CPU_DMA4,
IRQ_CPU_DMA5,
IRQ_CPU_DMA6,
IRQ_CPU_DMA7,
IRQ_CPU_EXTERNAL0,
IRQ_CPU_EXTERNAL1,
IRQ_CPU_EXTERNAL2,
IRQ_CPU_EXTERNAL3,
IRQ_CPU_EXTERNAL4,
IRQ_CPU_EXTERNAL5,
IRQ_CPU_EXTERNAL6,
IRQ_CPU_EXTERNAL7,
};
/* IRQ to level mappings */
#define IRQ_GDBSTUB_LEVEL 15
#define IRQ_UART_LEVEL 13
......@@ -82,6 +52,30 @@ enum {
#define IRQ_XIRQ6_LEVEL 7
#define IRQ_XIRQ7_LEVEL 8
/* IRQ IDs presented to drivers */
#define IRQ_CPU__UNUSED IRQ_BASE_CPU
#define IRQ_CPU_UART0 (IRQ_BASE_CPU + IRQ_UART0_LEVEL)
#define IRQ_CPU_UART1 (IRQ_BASE_CPU + IRQ_UART1_LEVEL)
#define IRQ_CPU_TIMER0 (IRQ_BASE_CPU + IRQ_TIMER0_LEVEL)
#define IRQ_CPU_TIMER1 (IRQ_BASE_CPU + IRQ_TIMER1_LEVEL)
#define IRQ_CPU_TIMER2 (IRQ_BASE_CPU + IRQ_TIMER2_LEVEL)
#define IRQ_CPU_DMA0 (IRQ_BASE_CPU + IRQ_DMA0_LEVEL)
#define IRQ_CPU_DMA1 (IRQ_BASE_CPU + IRQ_DMA1_LEVEL)
#define IRQ_CPU_DMA2 (IRQ_BASE_CPU + IRQ_DMA2_LEVEL)
#define IRQ_CPU_DMA3 (IRQ_BASE_CPU + IRQ_DMA3_LEVEL)
#define IRQ_CPU_DMA4 (IRQ_BASE_CPU + IRQ_DMA4_LEVEL)
#define IRQ_CPU_DMA5 (IRQ_BASE_CPU + IRQ_DMA5_LEVEL)
#define IRQ_CPU_DMA6 (IRQ_BASE_CPU + IRQ_DMA6_LEVEL)
#define IRQ_CPU_DMA7 (IRQ_BASE_CPU + IRQ_DMA7_LEVEL)
#define IRQ_CPU_EXTERNAL0 (IRQ_BASE_CPU + IRQ_XIRQ0_LEVEL)
#define IRQ_CPU_EXTERNAL1 (IRQ_BASE_CPU + IRQ_XIRQ1_LEVEL)
#define IRQ_CPU_EXTERNAL2 (IRQ_BASE_CPU + IRQ_XIRQ2_LEVEL)
#define IRQ_CPU_EXTERNAL3 (IRQ_BASE_CPU + IRQ_XIRQ3_LEVEL)
#define IRQ_CPU_EXTERNAL4 (IRQ_BASE_CPU + IRQ_XIRQ4_LEVEL)
#define IRQ_CPU_EXTERNAL5 (IRQ_BASE_CPU + IRQ_XIRQ5_LEVEL)
#define IRQ_CPU_EXTERNAL6 (IRQ_BASE_CPU + IRQ_XIRQ6_LEVEL)
#define IRQ_CPU_EXTERNAL7 (IRQ_BASE_CPU + IRQ_XIRQ7_LEVEL)
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_CPU_IRQS_H */
......@@ -26,5 +26,10 @@ typedef struct {
#error SMP not available on FR-V
#endif /* CONFIG_SMP */
extern atomic_t irq_err_count;
static inline void ack_bad_irq(int irq)
{
atomic_inc(&irq_err_count);
}
#endif
/* irq-routing.h: multiplexed IRQ routing
*
* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef _ASM_IRQ_ROUTING_H
#define _ASM_IRQ_ROUTING_H
#ifndef __ASSEMBLY__
#include <linux/spinlock.h>
#include <asm/irq.h>
struct irq_source;
struct irq_level;
/*
* IRQ action distribution sets
*/
struct irq_group {
int first_irq; /* first IRQ distributed here */
void (*control)(struct irq_group *group, int index, int on);
struct irqaction *actions[NR_IRQ_ACTIONS_PER_GROUP]; /* IRQ action chains */
struct irq_source *sources[NR_IRQ_ACTIONS_PER_GROUP]; /* IRQ sources */
int disable_cnt[NR_IRQ_ACTIONS_PER_GROUP]; /* disable counts */
};
/*
* IRQ source manager
*/
struct irq_source {
struct irq_source *next;
struct irq_level *level;
const char *muxname;
volatile void __iomem *muxdata;
unsigned long irqmask;
void (*doirq)(struct irq_source *source);
};
/*
* IRQ level management (per CPU IRQ priority / entry vector)
*/
struct irq_level {
int usage;
int disable_count;
unsigned long flags; /* current IRQF_DISABLED and IRQF_SHARED settings */
spinlock_t lock;
struct irq_source *sources;
};
extern struct irq_level frv_irq_levels[16];
extern struct irq_group *irq_groups[NR_IRQ_GROUPS];
extern void frv_irq_route(struct irq_source *source, int irqlevel);
extern void frv_irq_route_external(struct irq_source *source, int irq);
extern void frv_irq_set_group(struct irq_group *group);
extern void distribute_irqs(struct irq_group *group, unsigned long irqmask);
extern void route_cpu_irqs(void);
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_IRQ_ROUTING_H */
/* irq.h: FRV IRQ definitions
*
* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
* Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
......@@ -12,32 +12,22 @@
#ifndef _ASM_IRQ_H_
#define _ASM_IRQ_H_
/*
* the system has an on-CPU PIC and another PIC on the FPGA and other PICs on other peripherals,
* so we do some routing in irq-routing.[ch] to reduce the number of false-positives seen by
* drivers
*/
/* this number is used when no interrupt has been assigned */
#define NO_IRQ (-1)
#define NR_IRQ_LOG2_ACTIONS_PER_GROUP 5
#define NR_IRQ_ACTIONS_PER_GROUP (1 << NR_IRQ_LOG2_ACTIONS_PER_GROUP)
#define NR_IRQ_GROUPS 4
#define NR_IRQS (NR_IRQ_ACTIONS_PER_GROUP * NR_IRQ_GROUPS)
#define NR_IRQS 48
#define IRQ_BASE_CPU (0 * 16)
#define IRQ_BASE_FPGA (1 * 16)
#define IRQ_BASE_MB93493 (2 * 16)
/* probe returns a 32-bit IRQ mask:-/ */
#define MIN_PROBE_IRQ (NR_IRQS - 32)
#define MIN_PROBE_IRQ (NR_IRQS - 32)
#ifndef __ASSEMBLY__
static inline int irq_canonicalize(int irq)
{
return irq;
}
extern void disable_irq_nosync(unsigned int irq);
extern void disable_irq(unsigned int irq);
extern void enable_irq(unsigned int irq);
#endif
#endif /* _ASM_IRQ_H_ */
......@@ -12,11 +12,9 @@
#ifndef _ASM_MB93091_FPGA_IRQS_H
#define _ASM_MB93091_FPGA_IRQS_H
#ifndef __ASSEMBLY__
#include <asm/irq-routing.h>
#include <asm/irq.h>
#define IRQ_BASE_FPGA (NR_IRQ_ACTIONS_PER_GROUP * 1)
#ifndef __ASSEMBLY__
/* IRQ IDs presented to drivers */
enum {
......
......@@ -12,11 +12,9 @@
#ifndef _ASM_MB93093_FPGA_IRQS_H
#define _ASM_MB93093_FPGA_IRQS_H
#ifndef __ASSEMBLY__
#include <asm/irq-routing.h>
#include <asm/irq.h>
#define IRQ_BASE_FPGA (NR_IRQ_ACTIONS_PER_GROUP * 1)
#ifndef __ASSEMBLY__
/* IRQ IDs presented to drivers */
enum {
......
......@@ -12,11 +12,9 @@
#ifndef _ASM_MB93493_IRQS_H
#define _ASM_MB93493_IRQS_H
#ifndef __ASSEMBLY__
#include <asm/irq-routing.h>
#include <asm/irq.h>
#define IRQ_BASE_MB93493 (NR_IRQ_ACTIONS_PER_GROUP * 2)
#ifndef __ASSEMBLY__
/* IRQ IDs presented to drivers */
enum {
......
......@@ -15,6 +15,7 @@
#include <asm/mb-regs.h>
#include <asm/mb93493-irqs.h>
#define __addr_MB93493(X) ((volatile unsigned long *)(__region_CS3 + (X)))
#define __get_MB93493(X) ({ *(volatile unsigned long *)(__region_CS3 + (X)); })
#define __set_MB93493(X,V) \
......@@ -26,6 +27,7 @@ do { \
#define __set_MB93493_STSR(X,V) __set_MB93493(0x3c0 + (X) * 4, (V))
#define MB93493_STSR_EN
#define __addr_MB93493_IQSR(X) __addr_MB93493(0x3d0 + (X) * 4)
#define __get_MB93493_IQSR(X) __get_MB93493(0x3d0 + (X) * 4)
#define __set_MB93493_IQSR(X,V) __set_MB93493(0x3d0 + (X) * 4, (V))
......
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