Commit 1beb6a7d authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by Paul Mackerras

[PATCH] powerpc: Experimental support for new G5 Macs (#2)

This adds some very basic support for the new machines, including the
Quad G5 (tested), and other new dual core based machines and iMac G5
iSight (untested). This is still experimental !  There is no thermal
control yet, there is no proper handing of MSIs, etc.. but it
boots, I have all 4 cores up on my machine. Compared to the previous
version of this patch, this one adds DART IOMMU support for the U4
chipset and thus should work fine on setups with more than 2Gb of RAM.
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent cd0c7f06
......@@ -300,6 +300,7 @@ config PPC_PMAC64
bool
depends on PPC_PMAC && POWER4
select U3_DART
select MPIC_BROKEN_U3
select GENERIC_TBSYNC
default y
......
......@@ -34,7 +34,7 @@
#ifdef DEBUG
#include <asm/udbg.h>
#define DBG(fmt...) udbg_printf(fmt)
#define DBG(fmt...) printk(fmt)
#else
#define DBG(fmt...)
#endif
......@@ -323,6 +323,7 @@ static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
addrs = (u32 *) get_property(node, "assigned-addresses", &proplen);
if (!addrs)
return;
DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
for (; proplen >= 20; proplen -= 20, addrs += 5) {
flags = pci_parse_of_flags(addrs[0]);
if (!flags)
......@@ -332,6 +333,9 @@ static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
if (!size)
continue;
i = addrs[0] & 0xff;
DBG(" base: %llx, size: %llx, i: %x\n",
(unsigned long long)base, (unsigned long long)size, i);
if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
} else if (i == dev->rom_base_reg) {
......@@ -362,6 +366,8 @@ struct pci_dev *of_create_pci_dev(struct device_node *node,
if (type == NULL)
type = "";
DBG(" create device, devfn: %x, type: %s\n", devfn, type);
memset(dev, 0, sizeof(struct pci_dev));
dev->bus = bus;
dev->sysdata = node;
......@@ -381,6 +387,8 @@ struct pci_dev *of_create_pci_dev(struct device_node *node,
dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
dev->class = get_int_prop(node, "class-code", 0);
DBG(" class: 0x%x\n", dev->class);
dev->current_state = 4; /* unknown power state */
if (!strcmp(type, "pci")) {
......@@ -402,6 +410,8 @@ struct pci_dev *of_create_pci_dev(struct device_node *node,
pci_parse_of_addrs(node, dev);
DBG(" adding to system ...\n");
pci_device_add(dev, bus);
/* XXX pci_scan_msi_device(dev); */
......@@ -418,15 +428,21 @@ void __devinit of_scan_bus(struct device_node *node,
int reglen, devfn;
struct pci_dev *dev;
DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
while ((child = of_get_next_child(node, child)) != NULL) {
DBG(" * %s\n", child->full_name);
reg = (u32 *) get_property(child, "reg", &reglen);
if (reg == NULL || reglen < 20)
continue;
devfn = (reg[0] >> 8) & 0xff;
/* create a new pci_dev for this device */
dev = of_create_pci_dev(child, bus, devfn);
if (!dev)
continue;
DBG("dev header type: %x\n", dev->hdr_type);
if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
of_scan_pci_bridge(child, dev);
......@@ -446,16 +462,18 @@ void __devinit of_scan_pci_bridge(struct device_node *node,
unsigned int flags;
u64 size;
DBG("of_scan_pci_bridge(%s)\n", node->full_name);
/* parse bus-range property */
busrange = (u32 *) get_property(node, "bus-range", &len);
if (busrange == NULL || len != 8) {
printk(KERN_ERR "Can't get bus-range for PCI-PCI bridge %s\n",
printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
node->full_name);
return;
}
ranges = (u32 *) get_property(node, "ranges", &len);
if (ranges == NULL) {
printk(KERN_ERR "Can't get ranges for PCI-PCI bridge %s\n",
printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
node->full_name);
return;
}
......@@ -509,10 +527,13 @@ void __devinit of_scan_pci_bridge(struct device_node *node,
}
sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
bus->number);
DBG(" bus name: %s\n", bus->name);
mode = PCI_PROBE_NORMAL;
if (ppc_md.pci_probe_mode)
mode = ppc_md.pci_probe_mode(bus);
DBG(" probe mode: %d\n", mode);
if (mode == PCI_PROBE_DEVTREE)
of_scan_bus(node, bus);
else if (mode == PCI_PROBE_NORMAL)
......@@ -528,6 +549,8 @@ void __devinit scan_phb(struct pci_controller *hose)
int i, mode;
struct resource *res;
DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node);
if (bus == NULL) {
printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
......@@ -552,8 +575,9 @@ void __devinit scan_phb(struct pci_controller *hose)
mode = PCI_PROBE_NORMAL;
#ifdef CONFIG_PPC_MULTIPLATFORM
if (ppc_md.pci_probe_mode)
if (node && ppc_md.pci_probe_mode)
mode = ppc_md.pci_probe_mode(bus);
DBG(" probe mode: %d\n", mode);
if (mode == PCI_PROBE_DEVTREE) {
bus->subordinate = hose->last_busno;
of_scan_bus(node, bus);
......@@ -842,8 +866,7 @@ pgprot_t pci_phys_mem_access_prot(struct file *file,
* Returns a negative error code on failure, zero on success.
*/
int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
enum pci_mmap_state mmap_state,
int write_combine)
enum pci_mmap_state mmap_state, int write_combine)
{
unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
struct resource *rp;
......
......@@ -298,6 +298,16 @@ static int __devinit finish_node_interrupts(struct device_node *np,
int i, j, n, sense;
unsigned int *irq, virq;
struct device_node *ic;
int trace = 0;
//#define TRACE(fmt...) do { if (trace) { printk(fmt); mdelay(1000); } } while(0)
#define TRACE(fmt...)
if (!strcmp(np->name, "smu-doorbell"))
trace = 1;
TRACE("Finishing SMU doorbell ! num_interrupt_controllers = %d\n",
num_interrupt_controllers);
if (num_interrupt_controllers == 0) {
/*
......@@ -332,11 +342,12 @@ static int __devinit finish_node_interrupts(struct device_node *np,
}
ints = (unsigned int *) get_property(np, "interrupts", &intlen);
TRACE("ints=%p, intlen=%d\n", ints, intlen);
if (ints == NULL)
return 0;
intrcells = prom_n_intr_cells(np);
intlen /= intrcells * sizeof(unsigned int);
TRACE("intrcells=%d, new intlen=%d\n", intrcells, intlen);
np->intrs = prom_alloc(intlen * sizeof(*(np->intrs)), mem_start);
if (!np->intrs)
return -ENOMEM;
......@@ -347,6 +358,7 @@ static int __devinit finish_node_interrupts(struct device_node *np,
intrcount = 0;
for (i = 0; i < intlen; ++i, ints += intrcells) {
n = map_interrupt(&irq, &ic, np, ints, intrcells);
TRACE("map, irq=%d, ic=%p, n=%d\n", irq, ic, n);
if (n <= 0)
continue;
......@@ -357,6 +369,7 @@ static int __devinit finish_node_interrupts(struct device_node *np,
np->intrs[intrcount].sense = map_isa_senses[sense];
} else {
virq = virt_irq_create_mapping(irq[0]);
TRACE("virq=%d\n", virq);
#ifdef CONFIG_PPC64
if (virq == NO_IRQ) {
printk(KERN_CRIT "Could not allocate interrupt"
......@@ -366,6 +379,12 @@ static int __devinit finish_node_interrupts(struct device_node *np,
#endif
np->intrs[intrcount].line = irq_offset_up(virq);
sense = (n > 1)? (irq[1] & 3): 1;
/* Apple uses bits in there in a different way, let's
* only keep the real sense bit on macs
*/
if (_machine == PLATFORM_POWERMAC)
sense &= 0x1;
np->intrs[intrcount].sense = map_mpic_senses[sense];
}
......@@ -375,12 +394,13 @@ static int __devinit finish_node_interrupts(struct device_node *np,
char *name = get_property(ic->parent, "name", NULL);
if (name && !strcmp(name, "u3"))
np->intrs[intrcount].line += 128;
else if (!(name && !strcmp(name, "mac-io")))
else if (!(name && (!strcmp(name, "mac-io") ||
!strcmp(name, "u4"))))
/* ignore other cascaded controllers, such as
the k2-sata-root */
break;
}
#endif
#endif /* CONFIG_PPC64 */
if (n > 2) {
printk("hmmm, got %d intr cells for %s:", n,
np->full_name);
......
......@@ -110,10 +110,12 @@ static int early_console_initialized;
void __init disable_early_printk(void)
{
#if 1
if (!early_console_initialized)
return;
unregister_console(&udbg_console);
early_console_initialized = 0;
#endif
}
/* called by setup_system */
......
......@@ -195,7 +195,7 @@ static void __init maple_init_early(void)
/* Setup interrupt mapping options */
ppc64_interrupt_controller = IC_OPEN_PIC;
iommu_init_early_u3();
iommu_init_early_dart();
DBG(" <- maple_init_early\n");
}
......@@ -257,7 +257,7 @@ static int __init maple_probe(int platform)
* occupies having to be broken up so the DART itself is not
* part of the cacheable linar mapping
*/
alloc_u3_dart_table();
alloc_dart_table();
return 1;
}
......
......@@ -101,7 +101,8 @@ static const char *macio_names[] =
"Keylargo",
"Pangea",
"Intrepid",
"K2"
"K2",
"Shasta",
};
......@@ -119,7 +120,7 @@ static const char *macio_names[] =
static struct device_node *uninorth_node;
static u32 __iomem *uninorth_base;
static u32 uninorth_rev;
static int uninorth_u3;
static int uninorth_maj;
static void __iomem *u3_ht;
/*
......@@ -1399,8 +1400,15 @@ static long g5_fw_enable(struct device_node *node, long param, long value)
static long g5_mpic_enable(struct device_node *node, long param, long value)
{
unsigned long flags;
struct device_node *parent = of_get_parent(node);
int is_u3;
if (node->parent == NULL || strcmp(node->parent->name, "u3"))
if (parent == NULL)
return 0;
is_u3 = strcmp(parent->name, "u3") == 0 ||
strcmp(parent->name, "u4") == 0;
of_node_put(parent);
if (!is_u3)
return 0;
LOCK(flags);
......@@ -1464,7 +1472,7 @@ static long g5_i2s_enable(struct device_node *node, long param, long value)
},
};
if (macio->type != macio_keylargo2 /* && macio->type != macio_shasta*/)
if (macio->type != macio_keylargo2 && macio->type != macio_shasta)
return -ENODEV;
if (strncmp(node->name, "i2s-", 4))
return -ENODEV;
......@@ -1473,11 +1481,9 @@ static long g5_i2s_enable(struct device_node *node, long param, long value)
case 0:
case 1:
break;
#if 0
case 2:
if (macio->type == macio_shasta)
break;
#endif
default:
return -ENODEV;
}
......@@ -1508,7 +1514,7 @@ static long g5_reset_cpu(struct device_node *node, long param, long value)
struct device_node *np;
macio = &macio_chips[0];
if (macio->type != macio_keylargo2)
if (macio->type != macio_keylargo2 && macio->type != macio_shasta)
return -ENODEV;
np = find_path_device("/cpus");
......@@ -1547,7 +1553,8 @@ static long g5_reset_cpu(struct device_node *node, long param, long value)
*/
void g5_phy_disable_cpu1(void)
{
UN_OUT(U3_API_PHY_CONFIG_1, 0);
if (uninorth_maj == 3)
UN_OUT(U3_API_PHY_CONFIG_1, 0);
}
#endif /* CONFIG_POWER4 */
......@@ -2462,6 +2469,14 @@ static struct pmac_mb_def pmac_mb_defs[] = {
PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
0,
},
{ "PowerMac11,2", "PowerMac G5 Dual Core",
PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
0,
},
{ "PowerMac12,1", "iMac G5 (iSight)",
PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
0,
},
{ "RackMac3,1", "XServe G5",
PMAC_TYPE_XSERVE_G5, g5_features,
0,
......@@ -2574,6 +2589,11 @@ static int __init probe_motherboard(void)
pmac_mb.model_name = "Unknown K2-based";
pmac_mb.features = g5_features;
break;
case macio_shasta:
pmac_mb.model_id = PMAC_TYPE_UNKNOWN_SHASTA;
pmac_mb.model_name = "Unknown Shasta-based";
pmac_mb.features = g5_features;
break;
#endif /* CONFIG_POWER4 */
default:
return -ENODEV;
......@@ -2651,7 +2671,12 @@ static void __init probe_uninorth(void)
/* Locate G5 u3 */
if (uninorth_node == NULL) {
uninorth_node = of_find_node_by_name(NULL, "u3");
uninorth_u3 = 1;
uninorth_maj = 3;
}
/* Locate G5 u4 */
if (uninorth_node == NULL) {
uninorth_node = of_find_node_by_name(NULL, "u4");
uninorth_maj = 4;
}
if (uninorth_node == NULL)
return;
......@@ -2664,12 +2689,13 @@ static void __init probe_uninorth(void)
return;
uninorth_base = ioremap(address, 0x40000);
uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
if (uninorth_u3)
if (uninorth_maj == 3 || uninorth_maj == 4)
u3_ht = ioremap(address + U3_HT_CONFIG_BASE, 0x1000);
printk(KERN_INFO "Found %s memory controller & host bridge,"
" revision: %d\n", uninorth_u3 ? "U3" : "UniNorth",
uninorth_rev);
printk(KERN_INFO "Found %s memory controller & host bridge"
" @ 0x%08x revision: 0x%02x\n", uninorth_maj == 3 ? "U3" :
uninorth_maj == 4 ? "U4" : "UniNorth",
(unsigned int)address, uninorth_rev);
printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base);
/* Set the arbitrer QAck delay according to what Apple does
......@@ -2677,7 +2703,8 @@ static void __init probe_uninorth(void)
if (uninorth_rev < 0x11) {
actrl = UN_IN(UNI_N_ARB_CTRL) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK;
actrl |= ((uninorth_rev < 3) ? UNI_N_ARB_CTRL_QACK_DELAY105 :
UNI_N_ARB_CTRL_QACK_DELAY) << UNI_N_ARB_CTRL_QACK_DELAY_SHIFT;
UNI_N_ARB_CTRL_QACK_DELAY) <<
UNI_N_ARB_CTRL_QACK_DELAY_SHIFT;
UN_OUT(UNI_N_ARB_CTRL, actrl);
}
......@@ -2685,7 +2712,8 @@ static void __init probe_uninorth(void)
* revs 1.5 to 2.O and Pangea. Seem to toggle the UniN Maxbus/PCI
* memory timeout
*/
if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) || uninorth_rev == 0xc0)
if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) ||
uninorth_rev == 0xc0)
UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff);
}
......@@ -2736,12 +2764,14 @@ static void __init probe_one_macio(const char *name, const char *compat, int typ
node->full_name);
return;
}
if (type == macio_keylargo) {
if (type == macio_keylargo || type == macio_keylargo2) {
u32 *did = (u32 *)get_property(node, "device-id", NULL);
if (*did == 0x00000025)
type = macio_pangea;
if (*did == 0x0000003e)
type = macio_intrepid;
if (*did == 0x0000004f)
type = macio_shasta;
}
macio_chips[i].of_node = node;
macio_chips[i].type = type;
......@@ -2840,7 +2870,8 @@ set_initial_features(void)
}
#ifdef CONFIG_POWER4
if (macio_chips[0].type == macio_keylargo2) {
if (macio_chips[0].type == macio_keylargo2 ||
macio_chips[0].type == macio_shasta) {
#ifndef CONFIG_SMP
/* On SMP machines running UP, we have the second CPU eating
* bus cycles. We need to take it off the bus. This is done
......
This diff is collapsed.
......@@ -524,18 +524,56 @@ static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
#endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
}
static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
int master)
{
unsigned char senses[128];
int offset = master ? 0 : 128;
int count = master ? 128 : 124;
const char *name = master ? " MPIC 1 " : " MPIC 2 ";
struct resource r;
struct mpic *mpic;
unsigned int flags = master ? MPIC_PRIMARY : 0;
int rc;
rc = of_address_to_resource(np, 0, &r);
if (rc)
return NULL;
pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
prom_get_irq_senses(senses, offset, offset + count);
flags |= MPIC_WANTS_RESET;
if (get_property(np, "big-endian", NULL))
flags |= MPIC_BIG_ENDIAN;
/* Primary Big Endian means HT interrupts. This is quite dodgy
* but works until I find a better way
*/
if (master && (flags & MPIC_BIG_ENDIAN))
flags |= MPIC_BROKEN_U3;
mpic = mpic_alloc(r.start, flags, 0, offset, count, master ? 252 : 0,
senses, count, name);
if (mpic == NULL)
return NULL;
mpic_init(mpic);
return mpic;
}
static int __init pmac_pic_probe_mpic(void)
{
struct mpic *mpic1, *mpic2;
struct device_node *np, *master = NULL, *slave = NULL;
unsigned char senses[128];
struct resource r;
/* We can have up to 2 MPICs cascaded */
for (np = NULL; (np = of_find_node_by_type(np, "open-pic"))
!= NULL;) {
if (master == NULL &&
get_property(np, "interrupt-parent", NULL) != NULL)
get_property(np, "interrupts", NULL) == NULL)
master = of_node_get(np);
else if (slave == NULL)
slave = of_node_get(np);
......@@ -557,13 +595,8 @@ static int __init pmac_pic_probe_mpic(void)
ppc_md.get_irq = mpic_get_irq;
/* Setup master */
BUG_ON(of_address_to_resource(master, 0, &r));
pmac_call_feature(PMAC_FTR_ENABLE_MPIC, master, 0, 0);
prom_get_irq_senses(senses, 0, 128);
mpic1 = mpic_alloc(r.start, MPIC_PRIMARY | MPIC_WANTS_RESET,
0, 0, 128, 252, senses, 128, " OpenPIC ");
mpic1 = pmac_setup_one_mpic(master, 1);
BUG_ON(mpic1 == NULL);
mpic_init(mpic1);
/* Install NMI if any */
pmac_pic_setup_mpic_nmi(mpic1);
......@@ -574,27 +607,12 @@ static int __init pmac_pic_probe_mpic(void)
if (slave == NULL || slave->n_intrs < 1)
return 0;
/* Setup slave, failures are non-fatal */
if (of_address_to_resource(slave, 0, &r)) {
printk(KERN_ERR "Can't get address of MPIC %s\n",
slave->full_name);
return 0;
}
pmac_call_feature(PMAC_FTR_ENABLE_MPIC, slave, 0, 0);
prom_get_irq_senses(senses, 128, 128 + 124);
/* We don't need to set MPIC_BROKEN_U3 here since we don't have
* hypertransport interrupts routed to it, at least not on currently
* supported machines, that may change.
*/
mpic2 = mpic_alloc(r.start, MPIC_BIG_ENDIAN | MPIC_WANTS_RESET,
0, 128, 124, 0, senses, 124, " U3-MPIC ");
mpic2 = pmac_setup_one_mpic(slave, 0);
if (mpic2 == NULL) {
printk(KERN_ERR "Can't create slave MPIC %s\n",
slave->full_name);
printk(KERN_ERR "Failed to setup slave MPIC\n");
of_node_put(slave);
return 0;
}
mpic_init(mpic2);
mpic_setup_cascade(slave->intrs[0].line, pmac_u3_cascade, mpic2);
of_node_put(slave);
......
......@@ -345,7 +345,7 @@ void __init pmac_setup_arch(void)
#ifdef CONFIG_SMP
/* Check for Core99 */
if (find_devices("uni-n") || find_devices("u3"))
if (find_devices("uni-n") || find_devices("u3") || find_devices("u4"))
smp_ops = &core99_smp_ops;
#ifdef CONFIG_PPC32
else
......@@ -635,7 +635,7 @@ static void __init pmac_init_early(void)
/* Setup interrupt mapping options */
ppc64_interrupt_controller = IC_OPEN_PIC;
iommu_init_early_u3();
iommu_init_early_dart();
#endif
}
......@@ -711,7 +711,7 @@ static int __init pmac_probe(int platform)
* occupies having to be broken up so the DART itself is not
* part of the cacheable linar mapping
*/
alloc_u3_dart_table();
alloc_dart_table();
#endif
#ifdef CONFIG_PMAC_SMU
......@@ -733,10 +733,11 @@ static int pmac_pci_probe_mode(struct pci_bus *bus)
struct device_node *node = bus->sysdata;
/* We need to use normal PCI probing for the AGP bus,
since the device for the AGP bridge isn't in the tree. */
if (bus->self == NULL && device_is_compatible(node, "u3-agp"))
* since the device for the AGP bridge isn't in the tree.
*/
if (bus->self == NULL && (device_is_compatible(node, "u3-agp") ||
device_is_compatible(node, "u4-pcie")))
return PCI_PROBE_NORMAL;
return PCI_PROBE_DEVTREE;
}
#endif
......
This diff is collapsed.
......@@ -4,6 +4,6 @@ obj-$(CONFIG_PPC_I8259) += i8259.o
obj-$(CONFIG_PPC_MPC106) += grackle.o
obj-$(CONFIG_BOOKE) += dcr.o
obj-$(CONFIG_40x) += dcr.o
obj-$(CONFIG_U3_DART) += u3_iommu.o
obj-$(CONFIG_U3_DART) += dart_iommu.o
obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_83xx) += ipic.o
......@@ -20,29 +20,44 @@
#define _POWERPC_SYSDEV_DART_H
/* physical base of DART registers */
#define DART_BASE 0xf8033000UL
/* Offset from base to control register */
#define DARTCNTL 0
#define DART_CNTL 0
/* Offset from base to exception register */
#define DARTEXCP 0x10
#define DART_EXCP_U3 0x10
/* Offset from base to TLB tag registers */
#define DARTTAG 0x1000
#define DART_TAGS_U3 0x1000
/* U4 registers */
#define DART_BASE_U4 0x10
#define DART_SIZE_U4 0x20
#define DART_EXCP_U4 0x30
#define DART_TAGS_U4 0x1000
/* Control Register fields */
/* base address of table (pfn) */
#define DARTCNTL_BASE_MASK 0xfffff
#define DARTCNTL_BASE_SHIFT 12
/* U3 registers */
#define DART_CNTL_U3_BASE_MASK 0xfffff
#define DART_CNTL_U3_BASE_SHIFT 12
#define DART_CNTL_U3_FLUSHTLB 0x400
#define DART_CNTL_U3_ENABLE 0x200
#define DART_CNTL_U3_SIZE_MASK 0x1ff
#define DART_CNTL_U3_SIZE_SHIFT 0
/* U4 registers */
#define DART_BASE_U4_BASE_MASK 0xffffff
#define DART_BASE_U4_BASE_SHIFT 0
#define DART_CNTL_U4_FLUSHTLB 0x20000000
#define DART_CNTL_U4_ENABLE 0x80000000
#define DART_SIZE_U4_SIZE_MASK 0x1fff
#define DART_SIZE_U4_SIZE_SHIFT 0
#define DART_REG(r) (dart + ((r) >> 2))
#define DART_IN(r) (in_be32(DART_REG(r)))
#define DART_OUT(r,v) (out_be32(DART_REG(r), (v)))
#define DARTCNTL_FLUSHTLB 0x400
#define DARTCNTL_ENABLE 0x200
/* size of table in pages */
#define DARTCNTL_SIZE_MASK 0x1ff
#define DARTCNTL_SIZE_SHIFT 0
/* DART table fields */
......
This diff is collapsed.
......@@ -1686,7 +1686,7 @@ pmac_ide_probe(void)
#else
macio_register_driver(&pmac_ide_macio_driver);
pci_register_driver(&pmac_ide_pci_driver);
#endif
#endif
}
#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
......
......@@ -53,7 +53,7 @@
#undef DEBUG_SMU
#ifdef DEBUG_SMU
#define DPRINTK(fmt, args...) do { udbg_printf(KERN_DEBUG fmt , ##args); } while (0)
#define DPRINTK(fmt, args...) do { printk(KERN_DEBUG fmt , ##args); } while (0)
#else
#define DPRINTK(fmt, args...) do { } while (0)
#endif
......@@ -909,10 +909,13 @@ static struct smu_sdbp_header *smu_create_sdb_partition(int id)
struct property *prop;
/* First query the partition info */
DPRINTK("SMU: Query partition infos ... (irq=%d)\n", smu->db_irq);
smu_queue_simple(&cmd, SMU_CMD_PARTITION_COMMAND, 2,
smu_done_complete, &comp,
SMU_CMD_PARTITION_LATEST, id);
wait_for_completion(&comp);
DPRINTK("SMU: done, status: %d, reply_len: %d\n",
cmd.cmd.status, cmd.cmd.reply_len);
/* Partition doesn't exist (or other error) */
if (cmd.cmd.status != 0 || cmd.cmd.reply_len != 6)
......@@ -975,6 +978,8 @@ struct smu_sdbp_header *__smu_get_sdb_partition(int id, unsigned int *size,
sprintf(pname, "sdb-partition-%02x", id);
DPRINTK("smu_get_sdb_partition(%02x)\n", id);
if (interruptible) {
int rc;
rc = down_interruptible(&smu_part_access);
......@@ -986,6 +991,7 @@ struct smu_sdbp_header *__smu_get_sdb_partition(int id, unsigned int *size,
part = (struct smu_sdbp_header *)get_property(smu->of_node,
pname, size);
if (part == NULL) {
DPRINTK("trying to extract from SMU ...\n");
part = smu_create_sdb_partition(id);
if (part != NULL && size)
*size = part->len << 2;
......
......@@ -56,7 +56,7 @@ struct device_node;
/* Walks all buses and creates iommu tables */
extern void iommu_setup_pSeries(void);
extern void iommu_setup_u3(void);
extern void iommu_setup_dart(void);
/* Frees table for an individual device node */
extern void iommu_free_table(struct device_node *dn);
......@@ -104,7 +104,7 @@ extern void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle,
extern void iommu_init_early_pSeries(void);
extern void iommu_init_early_iSeries(void);
extern void iommu_init_early_u3(void);
extern void iommu_init_early_dart(void);
#ifdef CONFIG_PCI
extern void pci_iommu_init(void);
......@@ -113,6 +113,6 @@ extern void pci_direct_iommu_init(void);
static inline void pci_iommu_init(void) { }
#endif
extern void alloc_u3_dart_table(void);
extern void alloc_dart_table(void);
#endif /* _ASM_IOMMU_H */
......@@ -117,8 +117,9 @@ typedef int (*mpic_cascade_t)(struct pt_regs *regs, void *data);
struct mpic_irq_fixup
{
u8 __iomem *base;
u8 __iomem *applebase;
u32 data;
unsigned int irq;
unsigned int index;
};
#endif /* CONFIG_MPIC_BROKEN_U3 */
......
......@@ -121,6 +121,7 @@
#define PMAC_TYPE_IMAC_G5 0x152 /* iMac G5 */
#define PMAC_TYPE_XSERVE_G5 0x153 /* Xserve G5 */
#define PMAC_TYPE_UNKNOWN_K2 0x19f /* Any other K2 based */
#define PMAC_TYPE_UNKNOWN_SHASTA 0x19e /* Any other Shasta based */
/*
* Motherboard flags
......@@ -341,6 +342,7 @@ enum {
macio_pangea,
macio_intrepid,
macio_keylargo2,
macio_shasta,
};
struct macio_chip
......
......@@ -196,6 +196,7 @@
#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
#define PCI_CAP_ID_HT_IRQCONF 0x08 /* HyperTransport IRQ Configuration */
#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
......
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