Commit 1c16ae65 authored by Sean Wang's avatar Sean Wang Committed by Greg Kroah-Hartman

serial: 8250: of: Add new port type for MediaTek BTIF controller on MT7622/23 SoC

MediaTek BTIF controller is the serial interface similar to UART but it
works only as the digital device which is mainly used to communicate with
the connectivity module called CONNSYS inside the SoC which could be mostly
found on those MediaTek SoCs with Bluetooth feature such as MT7622 and
MT7623 SoCs.

And the controller is made as being compatible with the 8250 register
layout with extra registers such as DMA enablement so it tends to be
integrated with reusing 8250 OF driver. However, DMA mode is not being
supported yet in the current driver.
Signed-off-by: default avatarSean Wang <sean.wang@mediatek.com>
Suggested-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 785704d2
...@@ -313,6 +313,8 @@ static const struct of_device_id of_platform_serial_table[] = { ...@@ -313,6 +313,8 @@ static const struct of_device_id of_platform_serial_table[] = {
.data = (void *)PORT_ALTR_16550_F64, }, .data = (void *)PORT_ALTR_16550_F64, },
{ .compatible = "altr,16550-FIFO128", { .compatible = "altr,16550-FIFO128",
.data = (void *)PORT_ALTR_16550_F128, }, .data = (void *)PORT_ALTR_16550_F128, },
{ .compatible = "mediatek,mtk-btif",
.data = (void *)PORT_MTK_BTIF, },
{ .compatible = "mrvl,mmp-uart", { .compatible = "mrvl,mmp-uart",
.data = (void *)PORT_XSCALE, }, .data = (void *)PORT_XSCALE, },
{ .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, }, { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },
......
...@@ -289,6 +289,14 @@ static const struct serial8250_config uart_config[] = { ...@@ -289,6 +289,14 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {1, 4, 8, 14}, .rxtrig_bytes = {1, 4, 8, 14},
.flags = UART_CAP_FIFO | UART_CAP_AFE, .flags = UART_CAP_FIFO | UART_CAP_AFE,
}, },
[PORT_MTK_BTIF] = {
.name = "MediaTek BTIF",
.fifo_size = 16,
.tx_loadsz = 16,
.fcr = UART_FCR_ENABLE_FIFO |
UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
.flags = UART_CAP_FIFO,
},
}; };
/* Uart divisor latch read */ /* Uart divisor latch read */
......
...@@ -274,4 +274,7 @@ ...@@ -274,4 +274,7 @@
/* MPS2 UART */ /* MPS2 UART */
#define PORT_MPS2UART 116 #define PORT_MPS2UART 116
/* MediaTek BTIF */
#define PORT_MTK_BTIF 117
#endif /* _UAPILINUX_SERIAL_CORE_H */ #endif /* _UAPILINUX_SERIAL_CORE_H */
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