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Commit 1c75a78a authored by Andrzej Hajda's avatar Andrzej Hajda Committed by Kukjin Kim
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ARM: dts: use macros in clock bindings for exynos4 

The patch replaces magic numbers with macros defined in DT header
in exynos4 clock bindings.
Signed-off-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: default avatarKyungmin Park <kyungmin.park@samsung.com>
Acked-by: default avatarTomasz Figa <t.figa@samsung.com>
Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent d726ca2d
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Showing with 69 additions and 306 deletions
Documentation/devicetree/bindings/clock/exynos4-clock.txt
View file @ 1c75a78a
......@@ -15,259 +15,12 @@ Required Properties:
- #clock-cells: should be 1.
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume. Some of the clocks are available only on a particular
Exynos4 SoC and this is specified where applicable.
[Core Clocks]
Clock ID SoC (if specific)
-----------------------------------------------
xxti 1
xusbxti 2
fin_pll 3
fout_apll 4
fout_mpll 5
fout_epll 6
fout_vpll 7
sclk_apll 8
sclk_mpll 9
sclk_epll 10
sclk_vpll 11
arm_clk 12
aclk200 13
aclk100 14
aclk160 15
aclk133 16
mout_mpll_user_t 17 Exynos4x12
mout_mpll_user_c 18 Exynos4x12
mout_core 19
mout_apll 20
[Clock Gate for Special Clocks]
Clock ID SoC (if specific)
-----------------------------------------------
sclk_fimc0 128
sclk_fimc1 129
sclk_fimc2 130
sclk_fimc3 131
sclk_cam0 132
sclk_cam1 133
sclk_csis0 134
sclk_csis1 135
sclk_hdmi 136
sclk_mixer 137
sclk_dac 138
sclk_pixel 139
sclk_fimd0 140
sclk_mdnie0 141 Exynos4412
sclk_mdnie_pwm0 12 142 Exynos4412
sclk_mipi0 143
sclk_audio0 144
sclk_mmc0 145
sclk_mmc1 146
sclk_mmc2 147
sclk_mmc3 148
sclk_mmc4 149
sclk_sata 150 Exynos4210
sclk_uart0 151
sclk_uart1 152
sclk_uart2 153
sclk_uart3 154
sclk_uart4 155
sclk_audio1 156
sclk_audio2 157
sclk_spdif 158
sclk_spi0 159
sclk_spi1 160
sclk_spi2 161
sclk_slimbus 162
sclk_fimd1 163 Exynos4210
sclk_mipi1 164 Exynos4210
sclk_pcm1 165
sclk_pcm2 166
sclk_i2s1 167
sclk_i2s2 168
sclk_mipihsi 169 Exynos4412
sclk_mfc 170
sclk_pcm0 171
sclk_g3d 172
sclk_pwm_isp 173 Exynos4x12
sclk_spi0_isp 174 Exynos4x12
sclk_spi1_isp 175 Exynos4x12
sclk_uart_isp 176 Exynos4x12
sclk_fimg2d 177
[Peripheral Clock Gates]
Clock ID SoC (if specific)
-----------------------------------------------
fimc0 256
fimc1 257
fimc2 258
fimc3 259
csis0 260
csis1 261
jpeg 262
smmu_fimc0 263
smmu_fimc1 264
smmu_fimc2 265
smmu_fimc3 266
smmu_jpeg 267
vp 268
mixer 269
tvenc 270 Exynos4210
hdmi 271
smmu_tv 272
mfc 273
smmu_mfcl 274
smmu_mfcr 275
g3d 276
g2d 277
rotator 278 Exynos4210
mdma 279 Exynos4210
smmu_g2d 280 Exynos4210
smmu_rotator 281 Exynos4210
smmu_mdma 282 Exynos4210
fimd0 283
mie0 284
mdnie0 285 Exynos4412
dsim0 286
smmu_fimd0 287
fimd1 288 Exynos4210
mie1 289 Exynos4210
dsim1 290 Exynos4210
smmu_fimd1 291 Exynos4210
pdma0 292
pdma1 293
pcie_phy 294
sata_phy 295 Exynos4210
tsi 296
sdmmc0 297
sdmmc1 298
sdmmc2 299
sdmmc3 300
sdmmc4 301
sata 302 Exynos4210
sromc 303
usb_host 304
usb_device 305
pcie 306
onenand 307
nfcon 308
smmu_pcie 309
gps 310
smmu_gps 311
uart0 312
uart1 313
uart2 314
uart3 315
uart4 316
i2c0 317
i2c1 318
i2c2 319
i2c3 320
i2c4 321
i2c5 322
i2c6 323
i2c7 324
i2c_hdmi 325
tsadc 326
spi0 327
spi1 328
spi2 329
i2s1 330
i2s2 331
pcm0 332
i2s0 333
pcm1 334
pcm2 335
pwm 336
slimbus 337
spdif 338
ac97 339
modemif 340
chipid 341
sysreg 342
hdmi_cec 343
mct 344
wdt 345
rtc 346
keyif 347
audss 348
mipi_hsi 349 Exynos4210
mdma2 350 Exynos4210
pixelasyncm0 351
pixelasyncm1 352
fimc_lite0 353 Exynos4x12
fimc_lite1 354 Exynos4x12
ppmuispx 355 Exynos4x12
ppmuispmx 356 Exynos4x12
fimc_isp 357 Exynos4x12
fimc_drc 358 Exynos4x12
fimc_fd 359 Exynos4x12
mcuisp 360 Exynos4x12
gicisp 361 Exynos4x12
smmu_isp 362 Exynos4x12
smmu_drc 363 Exynos4x12
smmu_fd 364 Exynos4x12
smmu_lite0 365 Exynos4x12
smmu_lite1 366 Exynos4x12
mcuctl_isp 367 Exynos4x12
mpwm_isp 368 Exynos4x12
i2c0_isp 369 Exynos4x12
i2c1_isp 370 Exynos4x12
mtcadc_isp 371 Exynos4x12
pwm_isp 372 Exynos4x12
wdt_isp 373 Exynos4x12
uart_isp 374 Exynos4x12
asyncaxim 375 Exynos4x12
smmu_ispcx 376 Exynos4x12
spi0_isp 377 Exynos4x12
spi1_isp 378 Exynos4x12
pwm_isp_sclk 379 Exynos4x12
spi0_isp_sclk 380 Exynos4x12
spi1_isp_sclk 381 Exynos4x12
uart_isp_sclk 382 Exynos4x12
tmu_apbif 383
[Mux Clocks]
Clock ID SoC (if specific)
-----------------------------------------------
mout_fimc0 384
mout_fimc1 385
mout_fimc2 386
mout_fimc3 387
mout_cam0 388
mout_cam1 389
mout_csis0 390
mout_csis1 391
mout_g3d0 392
mout_g3d1 393
mout_g3d 394
aclk400_mcuisp 395 Exynos4x12
[Div Clocks]
Clock ID SoC (if specific)
-----------------------------------------------
div_isp0 450 Exynos4x12
div_isp1 451 Exynos4x12
div_mcuisp0 452 Exynos4x12
div_mcuisp1 453 Exynos4x12
div_aclk200 454 Exynos4x12
div_aclk400_mcuisp 455 Exynos4x12
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos4.h header and can be used in device
tree sources.
Example 1: An example of a clock controller node is listed below.
......@@ -285,6 +38,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
interrupts = <0 54 0>;
clocks = <&clock 314>, <&clock 153>;
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
};
arch/arm/boot/dts/exynos4.dtsi
View file @ 1c75a78a
This diff is collapsed.
arch/arm/boot/dts/exynos4210.dtsi
View file @ 1c75a78a
......@@ -53,7 +53,7 @@ mct@10050000 {
reg = <0x10050000 0x800>;
interrupt-parent = <&mct_map>;
interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
clocks = <&clock 3>, <&clock 344>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
mct_map: mct-map {
......@@ -109,7 +109,7 @@ tmu@100C0000 {
interrupt-parent = <&combiner>;
reg = <0x100C0000 0x100>;
interrupts = <2 4>;
clocks = <&clock 383>;
clocks = <&clock CLK_TMU_APBIF>;
clock-names = "tmu_apbif";
status = "disabled";
};
......@@ -118,13 +118,14 @@ g2d@12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
interrupts = <0 89 0>;
clocks = <&clock 177>, <&clock 277>;
clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
clock-names = "sclk_fimg2d", "fimg2d";
status = "disabled";
};
camera {
clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>;
clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
fimc_0: fimc@11800000 {
......
arch/arm/boot/dts/exynos4x12.dtsi
View file @ 1c75a78a
......@@ -47,7 +47,7 @@ mct@10050000 {
reg = <0x10050000 0x800>;
interrupt-parent = <&mct_map>;
interrupts = <0>, <1>, <2>, <3>, <4>;
clocks = <&clock 3>, <&clock 344>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
mct_map: mct-map {
......@@ -97,13 +97,14 @@ g2d@10800000 {
compatible = "samsung,exynos4212-g2d";
reg = <0x10800000 0x1000>;
interrupts = <0 89 0>;
clocks = <&clock 177>, <&clock 277>;
clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
clock-names = "sclk_fimg2d", "fimg2d";
status = "disabled";
};
camera {
clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>;
clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
fimc_0: fimc@11800000 {
......@@ -145,7 +146,7 @@ fimc_lite_0: fimc-lite@12390000 {
reg = <0x12390000 0x1000>;
interrupts = <0 105 0>;
samsung,power-domain = <&pd_isp>;
clocks = <&clock 353>;
clocks = <&clock CLK_FIMC_LITE0>;
clock-names = "flite";
status = "disabled";
};
......@@ -155,7 +156,7 @@ fimc_lite_1: fimc-lite@123A0000 {
reg = <0x123A0000 0x1000>;
interrupts = <0 106 0>;
samsung,power-domain = <&pd_isp>;
clocks = <&clock 354>;
clocks = <&clock CLK_FIMC_LITE1>;
clock-names = "flite";
status = "disabled";
};
......@@ -165,12 +166,19 @@ fimc_is: fimc-is@12000000 {
reg = <0x12000000 0x260000>;
interrupts = <0 90 0>, <0 95 0>;
samsung,power-domain = <&pd_isp>;
clocks = <&clock 353>, <&clock 354>, <&clock 355>,
<&clock 356>, <&clock 17>, <&clock 357>,
<&clock 358>, <&clock 359>, <&clock 360>,
<&clock 450>,<&clock 451>, <&clock 452>,
<&clock 453>, <&clock 176>, <&clock 13>,
<&clock 454>, <&clock 395>, <&clock 455>;
clocks = <&clock CLK_FIMC_LITE0>,
<&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
<&clock CLK_PPMUISPMX>,
<&clock CLK_MOUT_MPLL_USER_T>,
<&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
<&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
<&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
<&clock CLK_DIV_MCUISP0>,
<&clock CLK_DIV_MCUISP1>,
<&clock CLK_SCLK_UART_ISP>,
<&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
<&clock CLK_ACLK400_MCUISP>,
<&clock CLK_DIV_ACLK400_MCUISP>;
clock-names = "lite0", "lite1", "ppmuispx",
"ppmuispmx", "mpll", "isp",
"drc", "fd", "mcuisp",
......@@ -190,7 +198,7 @@ pmu {
i2c1_isp: i2c-isp@12140000 {
compatible = "samsung,exynos4212-i2c-isp";
reg = <0x12140000 0x100>;
clocks = <&clock 370>;
clocks = <&clock CLK_I2C1_ISP>;
clock-names = "i2c_isp";
#address-cells = <1>;
#size-cells = <0>;
......@@ -205,7 +213,7 @@ mshc_0: mmc@12550000 {
#address-cells = <1>;
#size-cells = <0>;
fifo-depth = <0x80>;
clocks = <&clock 301>, <&clock 149>;
clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
clock-names = "biu", "ciu";
status = "disabled";
};
......
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