Commit 1c810739 authored by Robin Murphy's avatar Robin Murphy Committed by Liviu Dudau

drm/arm/hdlcd: Allow a bit of clock tolerance

On the Arm Juno platform, the HDLCD pixel clock is constrained to 250KHz
resolution in order to avoid the tiny System Control Processor spending
aeons trying to calculate exact PLL coefficients. This means that modes
like my oddball 1600x1200 with 130.89MHz clock get rejected since the
rate cannot be matched exactly. In practice, though, this mode works
quite happily with the clock at 131MHz, so let's relax the check to
allow a little bit of slop.
Signed-off-by: default avatarRobin Murphy <robin.murphy@arm.com>
Signed-off-by: default avatarLiviu Dudau <liviu.dudau@arm.com>
parent b96151ed
...@@ -193,7 +193,8 @@ static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc, ...@@ -193,7 +193,8 @@ static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc,
long rate, clk_rate = mode->clock * 1000; long rate, clk_rate = mode->clock * 1000;
rate = clk_round_rate(hdlcd->clk, clk_rate); rate = clk_round_rate(hdlcd->clk, clk_rate);
if (rate != clk_rate) { /* 0.1% seems a close enough tolerance for the TDA19988 on Juno */
if (abs(rate - clk_rate) * 1000 > clk_rate) {
/* clock required by mode not supported by hardware */ /* clock required by mode not supported by hardware */
return MODE_NOCLOCK; return MODE_NOCLOCK;
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment