Commit 1e0c1ce0 authored by Andrew Lunn's avatar Andrew Lunn Committed by Arnd Bergmann

ARM: Orion: Fix WDT compile for Dove and MV78xx0

Commit 0fa1f060 (ARM: Orion: Fix
Virtual/Physical mixup with watchdog) broke the Dove & MV78xx0
build. Although these two SoC don't use the watchdog, the shared
platform code still needs to build. Add the necessary defines.

Cc: stable@vger.kernel.org
Reported-by: default avatarNicolas Pitre <nico@fluxnic.net>
Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
Tested-by: default avatarNicolas Pitre <nico@fluxnic.net>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent d19550e5
...@@ -50,5 +50,6 @@ ...@@ -50,5 +50,6 @@
#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c) #define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c)
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300)
#endif #endif
...@@ -78,6 +78,7 @@ ...@@ -78,6 +78,7 @@
/* North-South Bridge */ /* North-South Bridge */
#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x20000) #define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x20000)
#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x20000)
/* Cryptographic Engine */ /* Cryptographic Engine */
#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x30000) #define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x30000)
......
...@@ -31,5 +31,6 @@ ...@@ -31,5 +31,6 @@
#define IRQ_MASK_HIGH_OFF 0x0014 #define IRQ_MASK_HIGH_OFF 0x0014
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300)
#endif #endif
...@@ -42,6 +42,7 @@ ...@@ -42,6 +42,7 @@
#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 #define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000
#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
#define MV78XX0_CORE_REGS_SIZE SZ_16K #define MV78XX0_CORE_REGS_SIZE SZ_16K
#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
...@@ -59,6 +60,7 @@ ...@@ -59,6 +60,7 @@
* Core-specific peripheral registers. * Core-specific peripheral registers.
*/ */
#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE)
/* /*
* Register Map * Register Map
......
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