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Commit 1e36052e authored by Bruce Allan's avatar Bruce Allan Committed by Jeff Kirsher
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e1000e: cleanup indexed register arrays 

Some Rx and Tx specific registers are arrays indexed by the queue number.
For clarity, specify the intended queue rather than obscuring it behind a
define.
Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent c58c8a78
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Showing with 78 additions and 69 deletions
drivers/net/ethernet/intel/e1000e/ethtool.c
View file @ 1e36052e
......@@ -403,15 +403,15 @@ static void e1000_get_regs(struct net_device *netdev,
regs_buff[1] = er32(STATUS);
regs_buff[2] = er32(RCTL);
regs_buff[3] = er32(RDLEN);
regs_buff[4] = er32(RDH);
regs_buff[5] = er32(RDT);
regs_buff[3] = er32(RDLEN(0));
regs_buff[4] = er32(RDH(0));
regs_buff[5] = er32(RDT(0));
regs_buff[6] = er32(RDTR);
regs_buff[7] = er32(TCTL);
regs_buff[8] = er32(TDLEN);
regs_buff[9] = er32(TDH);
regs_buff[10] = er32(TDT);
regs_buff[8] = er32(TDLEN(0));
regs_buff[9] = er32(TDH(0));
regs_buff[10] = er32(TDT(0));
regs_buff[11] = er32(TIDV);
regs_buff[12] = adapter->hw.phy.type; /* PHY type (IGP=1, M88=0) */
......@@ -813,15 +813,15 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
}
REG_PATTERN_TEST(E1000_RDTR, 0x0000FFFF, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_RDLEN, 0x000FFF80, 0x000FFFFF);
REG_PATTERN_TEST(E1000_RDH, 0x0000FFFF, 0x0000FFFF);
REG_PATTERN_TEST(E1000_RDT, 0x0000FFFF, 0x0000FFFF);
REG_PATTERN_TEST(E1000_RDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_RDLEN(0), 0x000FFF80, 0x000FFFFF);
REG_PATTERN_TEST(E1000_RDH(0), 0x0000FFFF, 0x0000FFFF);
REG_PATTERN_TEST(E1000_RDT(0), 0x0000FFFF, 0x0000FFFF);
REG_PATTERN_TEST(E1000_FCRTH, 0x0000FFF8, 0x0000FFF8);
REG_PATTERN_TEST(E1000_FCTTV, 0x0000FFFF, 0x0000FFFF);
REG_PATTERN_TEST(E1000_TIPG, 0x3FFFFFFF, 0x3FFFFFFF);
REG_PATTERN_TEST(E1000_TDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_TDLEN, 0x000FFF80, 0x000FFFFF);
REG_PATTERN_TEST(E1000_TDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_TDLEN(0), 0x000FFF80, 0x000FFFFF);
REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x00000000);
......@@ -830,10 +830,10 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
REG_SET_AND_CHECK(E1000_TCTL, 0xFFFFFFFF, 0x00000000);
REG_SET_AND_CHECK(E1000_RCTL, before, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_RDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_RDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF);
if (!(adapter->flags & FLAG_IS_ICH))
REG_PATTERN_TEST(E1000_TXCW, 0xC000FFFF, 0x0000FFFF);
REG_PATTERN_TEST(E1000_TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_TDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF);
mask = 0x8003FFFF;
switch (mac->type) {
......@@ -1104,11 +1104,11 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
tx_ring->next_to_use = 0;
tx_ring->next_to_clean = 0;
ew32(TDBAL, ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
ew32(TDBAH, ((u64) tx_ring->dma >> 32));
ew32(TDLEN, tx_ring->count * sizeof(struct e1000_tx_desc));
ew32(TDH, 0);
ew32(TDT, 0);
ew32(TDBAL(0), ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
ew32(TDBAH(0), ((u64) tx_ring->dma >> 32));
ew32(TDLEN(0), tx_ring->count * sizeof(struct e1000_tx_desc));
ew32(TDH(0), 0);
ew32(TDT(0), 0);
ew32(TCTL, E1000_TCTL_PSP | E1000_TCTL_EN | E1000_TCTL_MULR |
E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
......@@ -1168,11 +1168,11 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
rctl = er32(RCTL);
if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
ew32(RCTL, rctl & ~E1000_RCTL_EN);
ew32(RDBAL, ((u64) rx_ring->dma & 0xFFFFFFFF));
ew32(RDBAH, ((u64) rx_ring->dma >> 32));
ew32(RDLEN, rx_ring->size);
ew32(RDH, 0);
ew32(RDT, 0);
ew32(RDBAL(0), ((u64) rx_ring->dma & 0xFFFFFFFF));
ew32(RDBAH(0), ((u64) rx_ring->dma >> 32));
ew32(RDLEN(0), rx_ring->size);
ew32(RDH(0), 0);
ew32(RDT(0), 0);
rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_LPE |
E1000_RCTL_SBP | E1000_RCTL_SECRC |
......@@ -1534,7 +1534,7 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter)
int ret_val = 0;
unsigned long time;
ew32(RDT, rx_ring->count - 1);
ew32(RDT(0), rx_ring->count - 1);
/*
* Calculate the loop count based on the largest descriptor ring
......@@ -1561,7 +1561,7 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter)
if (k == tx_ring->count)
k = 0;
}
ew32(TDT, k);
ew32(TDT(0), k);
e1e_flush();
msleep(200);
time = jiffies; /* set the start time for the receive */
......
drivers/net/ethernet/intel/e1000e/hw.h
View file @ 1e36052e
......@@ -94,31 +94,40 @@ enum e1e_registers {
E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
E1000_RDBAL = 0x02800, /* Rx Descriptor Base Address Low - RW */
E1000_RDBAH = 0x02804, /* Rx Descriptor Base Address High - RW */
E1000_RDLEN = 0x02808, /* Rx Descriptor Length - RW */
E1000_RDH = 0x02810, /* Rx Descriptor Head - RW */
E1000_RDT = 0x02818, /* Rx Descriptor Tail - RW */
E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */
E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
E1000_RADV = 0x0282C, /* Rx Interrupt Absolute Delay Timer - RW */
/* Convenience macros
/*
* Convenience macros
*
* Note: "_n" is the queue number of the register to be written to.
*
* Example usage:
* E1000_RDBAL_REG(current_rx_queue)
*
* E1000_RDBAL(current_rx_queue)
*/
#define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8))
E1000_RDBAL_BASE = 0x02800, /* Rx Descriptor Base Address Low - RW */
#define E1000_RDBAL(_n) (E1000_RDBAL_BASE + (_n << 8))
E1000_RDBAH_BASE = 0x02804, /* Rx Descriptor Base Address High - RW */
#define E1000_RDBAH(_n) (E1000_RDBAH_BASE + (_n << 8))
E1000_RDLEN_BASE = 0x02808, /* Rx Descriptor Length - RW */
#define E1000_RDLEN(_n) (E1000_RDLEN_BASE + (_n << 8))
E1000_RDH_BASE = 0x02810, /* Rx Descriptor Head - RW */
#define E1000_RDH(_n) (E1000_RDH_BASE + (_n << 8))
E1000_RDT_BASE = 0x02818, /* Rx Descriptor Tail - RW */
#define E1000_RDT(_n) (E1000_RDT_BASE + (_n << 8))
E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */
E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
E1000_RADV = 0x0282C, /* Rx Interrupt Absolute Delay Timer - RW */
E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
E1000_TDBAL = 0x03800, /* Tx Descriptor Base Address Low - RW */
E1000_TDBAH = 0x03804, /* Tx Descriptor Base Address High - RW */
E1000_TDLEN = 0x03808, /* Tx Descriptor Length - RW */
E1000_TDH = 0x03810, /* Tx Descriptor Head - RW */
E1000_TDT = 0x03818, /* Tx Descriptor Tail - RW */
E1000_TDBAL_BASE = 0x03800, /* Tx Descriptor Base Address Low - RW */
#define E1000_TDBAL(_n) (E1000_TDBAL_BASE + (_n << 8))
E1000_TDBAH_BASE = 0x03804, /* Tx Descriptor Base Address High - RW */
#define E1000_TDBAH(_n) (E1000_TDBAH_BASE + (_n << 8))
E1000_TDLEN_BASE = 0x03808, /* Tx Descriptor Length - RW */
#define E1000_TDLEN(_n) (E1000_TDLEN_BASE + (_n << 8))
E1000_TDH_BASE = 0x03810, /* Tx Descriptor Head - RW */
#define E1000_TDH(_n) (E1000_TDH_BASE + (_n << 8))
E1000_TDT_BASE = 0x03818, /* Tx Descriptor Tail - RW */
#define E1000_TDT(_n) (E1000_TDT_BASE + (_n << 8))
E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */
E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
#define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
......
drivers/net/ethernet/intel/e1000e/netdev.c
View file @ 1e36052e
......@@ -110,14 +110,14 @@ static const struct e1000_reg_info e1000_reg_info_tbl[] = {
/* Rx Registers */
{E1000_RCTL, "RCTL"},
{E1000_RDLEN, "RDLEN"},
{E1000_RDH, "RDH"},
{E1000_RDT, "RDT"},
{E1000_RDLEN(0), "RDLEN"},
{E1000_RDH(0), "RDH"},
{E1000_RDT(0), "RDT"},
{E1000_RDTR, "RDTR"},
{E1000_RXDCTL(0), "RXDCTL"},
{E1000_ERT, "ERT"},
{E1000_RDBAL, "RDBAL"},
{E1000_RDBAH, "RDBAH"},
{E1000_RDBAL(0), "RDBAL"},
{E1000_RDBAH(0), "RDBAH"},
{E1000_RDFH, "RDFH"},
{E1000_RDFT, "RDFT"},
{E1000_RDFHS, "RDFHS"},
......@@ -126,11 +126,11 @@ static const struct e1000_reg_info e1000_reg_info_tbl[] = {
/* Tx Registers */
{E1000_TCTL, "TCTL"},
{E1000_TDBAL, "TDBAL"},
{E1000_TDBAH, "TDBAH"},
{E1000_TDLEN, "TDLEN"},
{E1000_TDH, "TDH"},
{E1000_TDT, "TDT"},
{E1000_TDBAL(0), "TDBAL"},
{E1000_TDBAH(0), "TDBAH"},
{E1000_TDLEN(0), "TDLEN"},
{E1000_TDH(0), "TDH"},
{E1000_TDT(0), "TDT"},
{E1000_TIDV, "TIDV"},
{E1000_TXDCTL(0), "TXDCTL"},
{E1000_TADV, "TADV"},
......@@ -2792,13 +2792,13 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
/* Setup the HW Tx Head and Tail descriptor pointers */
tdba = tx_ring->dma;
tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
ew32(TDBAL, (tdba & DMA_BIT_MASK(32)));
ew32(TDBAH, (tdba >> 32));
ew32(TDLEN, tdlen);
ew32(TDH, 0);
ew32(TDT, 0);
tx_ring->head = adapter->hw.hw_addr + E1000_TDH;
tx_ring->tail = adapter->hw.hw_addr + E1000_TDT;
ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
ew32(TDBAH(0), (tdba >> 32));
ew32(TDLEN(0), tdlen);
ew32(TDH(0), 0);
ew32(TDT(0), 0);
tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
/* Set the Tx Interrupt Delay register */
ew32(TIDV, adapter->tx_int_delay);
......@@ -3102,13 +3102,13 @@ static void e1000_configure_rx(struct e1000_adapter *adapter)
* the Base and Length of the Rx Descriptor Ring
*/
rdba = rx_ring->dma;
ew32(RDBAL, (rdba & DMA_BIT_MASK(32)));
ew32(RDBAH, (rdba >> 32));
ew32(RDLEN, rdlen);
ew32(RDH, 0);
ew32(RDT, 0);
rx_ring->head = adapter->hw.hw_addr + E1000_RDH;
rx_ring->tail = adapter->hw.hw_addr + E1000_RDT;
ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
ew32(RDBAH(0), (rdba >> 32));
ew32(RDLEN(0), rdlen);
ew32(RDH(0), 0);
ew32(RDT(0), 0);
rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
/* Enable Receive Checksum Offload for TCP and UDP */
rxcsum = er32(RXCSUM);
......
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