Commit 1e4eccda authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher

drm/amdgpu: fix to miss program invalidation at resume

This patch moves invalidation into gart enable function from hw_init.
Because we would like align the sequence calling between init and resume.
Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3dff4cc4
...@@ -232,6 +232,20 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) ...@@ -232,6 +232,20 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
} }
} }
static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
{
unsigned i;
for (i = 0 ; i < 18; ++i) {
WREG32(SOC15_REG_OFFSET(GC, 0,
mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
2 * i, 0xffffffff);
WREG32(SOC15_REG_OFFSET(GC, 0,
mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
2 * i, 0x1f);
}
}
int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
{ {
if (amdgpu_sriov_vf(adev)) { if (amdgpu_sriov_vf(adev)) {
...@@ -255,6 +269,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) ...@@ -255,6 +269,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
gfxhub_v1_0_enable_system_domain(adev); gfxhub_v1_0_enable_system_domain(adev);
gfxhub_v1_0_disable_identity_aperture(adev); gfxhub_v1_0_disable_identity_aperture(adev);
gfxhub_v1_0_setup_vmid_config(adev); gfxhub_v1_0_setup_vmid_config(adev);
gfxhub_v1_0_program_invalidation(adev);
return 0; return 0;
} }
...@@ -364,18 +379,6 @@ static int gfxhub_v1_0_sw_fini(void *handle) ...@@ -364,18 +379,6 @@ static int gfxhub_v1_0_sw_fini(void *handle)
static int gfxhub_v1_0_hw_init(void *handle) static int gfxhub_v1_0_hw_init(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
unsigned i;
for (i = 0 ; i < 18; ++i) {
WREG32(SOC15_REG_OFFSET(GC, 0,
mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
2 * i, 0xffffffff);
WREG32(SOC15_REG_OFFSET(GC, 0,
mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
2 * i, 0x1f);
}
return 0; return 0;
} }
......
...@@ -244,6 +244,20 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) ...@@ -244,6 +244,20 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
} }
} }
static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
{
unsigned i;
for (i = 0; i < 18; ++i) {
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
2 * i, 0xffffffff);
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
2 * i, 0x1f);
}
}
int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
{ {
if (amdgpu_sriov_vf(adev)) { if (amdgpu_sriov_vf(adev)) {
...@@ -267,6 +281,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) ...@@ -267,6 +281,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
mmhub_v1_0_enable_system_domain(adev); mmhub_v1_0_enable_system_domain(adev);
mmhub_v1_0_disable_identity_aperture(adev); mmhub_v1_0_disable_identity_aperture(adev);
mmhub_v1_0_setup_vmid_config(adev); mmhub_v1_0_setup_vmid_config(adev);
mmhub_v1_0_program_invalidation(adev);
return 0; return 0;
} }
...@@ -375,18 +390,6 @@ static int mmhub_v1_0_sw_fini(void *handle) ...@@ -375,18 +390,6 @@ static int mmhub_v1_0_sw_fini(void *handle)
static int mmhub_v1_0_hw_init(void *handle) static int mmhub_v1_0_hw_init(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
unsigned i;
for (i = 0; i < 18; ++i) {
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
2 * i, 0xffffffff);
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
2 * i, 0x1f);
}
return 0; return 0;
} }
......
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