Commit 1e7bdf82 authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'mvebu-watchdog-3.15' of git://git.infradead.org/linux-mvebu into next/drivers

mvebu watchdog driver changes for v3.15

 - orion watchdog
    - cleanup and extend driver to support Armada 370 and Armada XP

Depends:
 - tags/irqchip-mvebu-fixes-3.14 (already pulled by tglx)
    - both are based on v3.14-rc1

* tag 'mvebu-watchdog-3.15' of git://git.infradead.org/linux-mvebu:
  watchdog: orion: Enable the build on ARCH_MVEBU
  watchdog: orion: Add support for Armada 370 and Armada XP SoC
  watchdog: orion: Add per-compatible watchdog start implementation
  watchdog: orion: Add per-compatible clock initialization
  watchdog: orion: Introduce per-compatible of_device_id data
  watchdog: orion: Introduce an orion_watchdog device structure
  watchdog: orion: Remove unneeded BRIDGE_CAUSE clear
  watchdog: orion: Make RSTOUT register a separate resource
  watchdog: orion: Handle the interrupt so it's properly acked
  watchdog: orion: Make sure the watchdog is initially stopped
  watchdog: orion: Remove unused macros
  watchdog: orion: Use atomic access for shared registers
  watchdog: orion: Add clock error handling
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 96f9d40d 59416745
......@@ -3,17 +3,24 @@
Required Properties:
- Compatibility : "marvell,orion-wdt"
- reg : Address of the timer registers
"marvell,armada-370-wdt"
"marvell,armada-xp-wdt"
- reg : Should contain two entries: first one with the
timer control address, second one with the
rstout enable address.
Optional properties:
- interrupts : Contains the IRQ for watchdog expiration
- timeout-sec : Contains the watchdog timeout in seconds
Example:
wdt@20300 {
compatible = "marvell,orion-wdt";
reg = <0x20300 0x28>;
reg = <0x20300 0x28>, <0x20108 0x4>;
interrupts = <3>;
timeout-sec = <10>;
status = "okay";
};
......@@ -21,6 +21,7 @@
#define CPU_CTRL_PCIE1_LINK 0x00000008
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
......
......@@ -21,6 +21,7 @@
#define CPU_RESET 0x00000002
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
......
......@@ -15,6 +15,7 @@
#define L2_WRITETHROUGH 0x00020000
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
......
......@@ -18,6 +18,7 @@
#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
#define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
......
......@@ -595,14 +595,16 @@ void __init orion_spi_1_init(unsigned long mapbase)
/*****************************************************************************
* Watchdog
****************************************************************************/
static struct resource orion_wdt_resource =
DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x28);
static struct resource orion_wdt_resource[] = {
DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
};
static struct platform_device orion_wdt_device = {
.name = "orion_wdt",
.id = -1,
.num_resources = 1,
.resource = &orion_wdt_resource,
.num_resources = ARRAY_SIZE(orion_wdt_resource),
.resource = orion_wdt_resource,
};
void __init orion_wdt_init(void)
......
......@@ -292,7 +292,7 @@ config DAVINCI_WATCHDOG
config ORION_WATCHDOG
tristate "Orion watchdog"
depends on ARCH_ORION5X || ARCH_KIRKWOOD || ARCH_DOVE
depends on ARCH_ORION5X || ARCH_KIRKWOOD || ARCH_DOVE || ARCH_MVEBU
select WATCHDOG_CORE
help
Say Y here if to include support for the watchdog timer
......
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