Commit 1f1496a9 authored by Damien Le Moal's avatar Damien Le Moal Committed by Palmer Dabbelt

riscv: Fix sifive serial driver

Setup the port uartclk in sifive_serial_probe() so that the base baud
rate is correctly printed during device probe instead of always showing
"0".  I.e. the probe message is changed from

38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1,
base_baud = 0) is a SiFive UART v0

to the correct:

38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1,
base_baud = 115200) is a SiFive UART v0
Signed-off-by: default avatarDamien Le Moal <damien.lemoal@wdc.com>
Reviewed-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
Acked-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent 11f4c2e9
......@@ -1000,6 +1000,7 @@ static int sifive_serial_probe(struct platform_device *pdev)
/* Set up clock divider */
ssp->clkin_rate = clk_get_rate(ssp->clk);
ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
ssp->port.uartclk = ssp->baud_rate * 16;
__ssp_update_div(ssp);
platform_set_drvdata(pdev, ssp);
......
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