Commit 1f73f31a authored by Viresh Kumar's avatar Viresh Kumar Committed by Mike Turquette

clk: Fix typo in comment

CLK_MUX_INDEX_BIT is mistakenly written as CLK_MUX_INDEX_BITWISE in comment. Fix
it.

CLK_GATE_SET_TO_DISABLE is mistakenly written as CLK_GATE_SET_DISABLE in
comment. Fix it.
Signed-off-by: default avatarViresh Kumar <viresh.kumar@st.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent f4d8af2e
...@@ -159,7 +159,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name, ...@@ -159,7 +159,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
* Clock which can gate its output. Implements .enable & .disable * Clock which can gate its output. Implements .enable & .disable
* *
* Flags: * Flags:
* CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
* enable the clock. Setting this flag does the opposite: setting the bit * enable the clock. Setting this flag does the opposite: setting the bit
* disable the clock and clearing it enables the clock * disable the clock and clearing it enables the clock
*/ */
...@@ -232,7 +232,7 @@ struct clk *clk_register_divider(struct device *dev, const char *name, ...@@ -232,7 +232,7 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
* *
* Flags: * Flags:
* CLK_MUX_INDEX_ONE - register index starts at 1, not 0 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
* CLK_MUX_INDEX_BITWISE - register index is a single bit (power of two) * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
*/ */
struct clk_mux { struct clk_mux {
struct clk_hw hw; struct clk_hw hw;
......
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