Commit 201a8df8 authored by Rob Herring's avatar Rob Herring Committed by Lorenzo Pieralisi

PCI: dwc/imx6: Use common PCI register definitions

The i.MX6 driver has its own defines for common PCI config space
registers. It also hard codes the capability register offsets which are
discoverable. Convert it to use the standard register definitions.

Link: https://lore.kernel.org/r/20200821035420.380495-29-robh@kernel.orgSigned-off-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
parent 2f2cea1e
...@@ -94,15 +94,6 @@ struct imx6_pcie { ...@@ -94,15 +94,6 @@ struct imx6_pcie {
#define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200
#define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX) #define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX)
/* PCIe Root Complex registers (memory-mapped) */
#define PCIE_RC_IMX6_MSI_CAP 0x50
#define PCIE_RC_LCR 0x7c
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
#define PCIE_RC_LCSR 0x80
/* PCIe Port Logic registers (memory-mapped) */ /* PCIe Port Logic registers (memory-mapped) */
#define PL_OFFSET 0x700 #define PL_OFFSET 0x700
...@@ -759,6 +750,7 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) ...@@ -759,6 +750,7 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
{ {
struct dw_pcie *pci = imx6_pcie->pci; struct dw_pcie *pci = imx6_pcie->pci;
struct device *dev = pci->dev; struct device *dev = pci->dev;
u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
u32 tmp; u32 tmp;
int ret; int ret;
...@@ -767,10 +759,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) ...@@ -767,10 +759,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
* started in Gen2 mode, there is a possibility the devices on the * started in Gen2 mode, there is a possibility the devices on the
* bus will not be detected at all. This happens with PCIe switches. * bus will not be detected at all. This happens with PCIe switches.
*/ */
tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR); tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; tmp &= ~PCI_EXP_LNKCAP_SLS;
tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
/* Start LTSSM. */ /* Start LTSSM. */
imx6_pcie_ltssm_enable(dev); imx6_pcie_ltssm_enable(dev);
...@@ -781,10 +773,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) ...@@ -781,10 +773,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
if (imx6_pcie->link_gen == 2) { if (imx6_pcie->link_gen == 2) {
/* Allow Gen2 mode after the link is up. */ /* Allow Gen2 mode after the link is up. */
tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR); tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; tmp &= ~PCI_EXP_LNKCAP_SLS;
tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; tmp |= PCI_EXP_LNKCAP_SLS_5_0GB;
dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
/* /*
* Start Directed Speed Change so the best possible * Start Directed Speed Change so the best possible
...@@ -822,8 +814,8 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) ...@@ -822,8 +814,8 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
dev_info(dev, "Link: Gen2 disabled\n"); dev_info(dev, "Link: Gen2 disabled\n");
} }
tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR); tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf); dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS);
return 0; return 0;
err_reset_phy: err_reset_phy:
...@@ -1184,11 +1176,10 @@ static int imx6_pcie_probe(struct platform_device *pdev) ...@@ -1184,11 +1176,10 @@ static int imx6_pcie_probe(struct platform_device *pdev)
return ret; return ret;
if (pci_msi_enabled()) { if (pci_msi_enabled()) {
val = dw_pcie_readw_dbi(pci, PCIE_RC_IMX6_MSI_CAP + u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
PCI_MSI_FLAGS); val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
val |= PCI_MSI_FLAGS_ENABLE; val |= PCI_MSI_FLAGS_ENABLE;
dw_pcie_writew_dbi(pci, PCIE_RC_IMX6_MSI_CAP + PCI_MSI_FLAGS, dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);
val);
} }
return 0; return 0;
......
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