Commit 218abe6f authored by Dirk Behme's avatar Dirk Behme Committed by Shawn Guo

ARM: dts: imx6q: add PMU

Add ARM Cortex A9 Performance Monitor Unit (PMU) support.
On i.MX6 a combined interrupt on hardware line #126 is used
(i.MX6 TRM: Performance Unit interrupt).

For more details see Documentation/devicetree/bindings/arm/pmu.txt
Signed-off-by: default avatarDirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 8b9ad9f6
...@@ -101,6 +101,11 @@ L2: l2-cache@00a02000 { ...@@ -101,6 +101,11 @@ L2: l2-cache@00a02000 {
cache-level = <2>; cache-level = <2>;
}; };
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 94 0x04>;
};
aips-bus@02000000 { /* AIPS1 */ aips-bus@02000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus"; compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>; #address-cells = <1>;
......
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