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Commit 21d638ef authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
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MIPS: TXX9: Remove rbtx4938 board support 

No active MIPS user own this board, so let's remove it.
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
Reviewed-by: default avatarGeert Uytterhoeven <geert@linux-m68k.org>
Tested-by: default avatarGeert Uytterhoeven <geert@linux-m68k.org>
parent f2c6c22f
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arch/mips/configs/rbtx49xx_defconfig
View file @ 21d638ef
......@@ -10,9 +10,7 @@ CONFIG_EXPERT=y
CONFIG_SLAB=y
CONFIG_MACH_TX49XX=y
CONFIG_TOSHIBA_RBTX4927=y
CONFIG_TOSHIBA_RBTX4938=y
CONFIG_TOSHIBA_RBTX4939=y
CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP=y
# CONFIG_SECCOMP is not set
CONFIG_PCI=y
CONFIG_MODULES=y
......
arch/mips/include/asm/txx9/boards.h
View file @ 21d638ef
......@@ -6,9 +6,6 @@ BOARD_VEC(jmr3927_vec)
BOARD_VEC(rbtx4927_vec)
BOARD_VEC(rbtx4937_vec)
#endif
#ifdef CONFIG_TOSHIBA_RBTX4938
BOARD_VEC(rbtx4938_vec)
#endif
#ifdef CONFIG_TOSHIBA_RBTX4939
BOARD_VEC(rbtx4939_vec)
#endif
arch/mips/include/asm/txx9/rbtx4938.h deleted 100644 → 0
View file @ f2c6c22f
/*
* Definitions for TX4937/TX4938
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#ifndef __ASM_TXX9_RBTX4938_H
#define __ASM_TXX9_RBTX4938_H
#include <asm/addrspace.h>
#include <asm/txx9irq.h>
#include <asm/txx9/tx4938.h>
/* Address map */
#define RBTX4938_FPGA_REG_ADDR (IO_BASE + TXX9_CE(2) + 0x00000000)
#define RBTX4938_FPGA_REV_ADDR (IO_BASE + TXX9_CE(2) + 0x00000002)
#define RBTX4938_CONFIG1_ADDR (IO_BASE + TXX9_CE(2) + 0x00000004)
#define RBTX4938_CONFIG2_ADDR (IO_BASE + TXX9_CE(2) + 0x00000006)
#define RBTX4938_CONFIG3_ADDR (IO_BASE + TXX9_CE(2) + 0x00000008)
#define RBTX4938_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
#define RBTX4938_DIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001002)
#define RBTX4938_BDIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001004)
#define RBTX4938_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
#define RBTX4938_IMASK2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002002)
#define RBTX4938_INTPOL_ADDR (IO_BASE + TXX9_CE(2) + 0x00002004)
#define RBTX4938_ISTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
#define RBTX4938_ISTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002008)
#define RBTX4938_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200a)
#define RBTX4938_IMSTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200c)
#define RBTX4938_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
#define RBTX4938_PIOSEL_ADDR (IO_BASE + TXX9_CE(2) + 0x00005000)
#define RBTX4938_SPICS_ADDR (IO_BASE + TXX9_CE(2) + 0x00005002)
#define RBTX4938_SFPWR_ADDR (IO_BASE + TXX9_CE(2) + 0x00005008)
#define RBTX4938_SFVOL_ADDR (IO_BASE + TXX9_CE(2) + 0x0000500a)
#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)
#define RBTX4938_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x00007002)
#define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004)
#define RBTX4938_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
/* Ethernet port address (Jumperless Mode (W12:Open)) */
#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280)
/* bits for ISTAT/IMASK/IMSTAT */
#define RBTX4938_INTB_PCID 0
#define RBTX4938_INTB_PCIC 1
#define RBTX4938_INTB_PCIB 2
#define RBTX4938_INTB_PCIA 3
#define RBTX4938_INTB_RTC 4
#define RBTX4938_INTB_ATA 5
#define RBTX4938_INTB_MODEM 6
#define RBTX4938_INTB_SWINT 7
#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID)
#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC)
#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB)
#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA)
#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC)
#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA)
#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM)
#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT)
#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR)
#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR)
#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR)
#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR)
#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR)
#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR)
#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR)
#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR)
#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR)
#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR)
#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR)
#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR)
#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR)
#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
#define rbtx4938_softresetlock_addr \
((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
/*
* IRQ mappings
*/
#define RBTX4938_SOFT_INT0 0 /* not used */
#define RBTX4938_SOFT_INT1 1 /* not used */
#define RBTX4938_IRC_INT 2
#define RBTX4938_TIMER_INT 7
/* These are the virtual IRQ numbers, we divide all IRQ's into
* 'spaces', the 'space' determines where and how to enable/disable
* that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
* IRQ hardware is supported.
*/
#define RBTX4938_NR_IRQ_IOC 8
#define RBTX4938_IRQ_IRC TXX9_IRQ_BASE
#define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR)
#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n))
#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
/* IOC (PCI, etc) */
#define RBTX4938_IRQ_IOCINT (TXX9_IRQ_BASE + TX4938_IR_INT(0))
/* Onboard 10M Ether */
#define RBTX4938_IRQ_ETHER (TXX9_IRQ_BASE + TX4938_IR_INT(1))
#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER)
void rbtx4938_prom_init(void);
void rbtx4938_irq_setup(void);
struct pci_dev;
int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
#endif /* __ASM_TXX9_RBTX4938_H */
arch/mips/include/asm/txx9/spi.h deleted 100644 → 0
View file @ f2c6c22f
/*
* Definitions for TX4937/TX4938 SPI
*
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#ifndef __ASM_TXX9_SPI_H
#define __ASM_TXX9_SPI_H
#include <linux/errno.h>
#ifdef CONFIG_SPI
int spi_eeprom_register(int busid, int chipid, int size);
int spi_eeprom_read(int busid, int chipid,
int address, unsigned char *buf, int len);
#else
static inline int spi_eeprom_register(int busid, int chipid, int size)
{
return -ENODEV;
}
static inline int spi_eeprom_read(int busid, int chipid,
int address, unsigned char *buf, int len)
{
return -ENODEV;
}
#endif
#endif /* __ASM_TXX9_SPI_H */
arch/mips/pci/Makefile
View file @ 21d638ef
......@@ -51,7 +51,6 @@ obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o
obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o
obj-$(CONFIG_SOC_TX4939) += pci-tx4939.o
obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o
obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o
obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
......
arch/mips/pci/fixup-rbtx4938.c deleted 100644 → 0
View file @ f2c6c22f
/*
* Toshiba rbtx4938 pci routines
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#include <linux/types.h>
#include <asm/txx9/pci.h>
#include <asm/txx9/rbtx4938.h>
int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq = tx4938_pcic1_map_irq(dev, slot);
if (irq >= 0)
return irq;
irq = pin;
/* IRQ rotation */
irq--; /* 0-3 */
if (slot == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) {
/* PCI CardSlot (IDSEL=A23) */
/* PCIA => PCIA (IDSEL=A23) */
irq = (irq + 0 + slot) % 4;
} else {
/* PCI Backplane */
if (txx9_pci_option & TXX9_PCI_OPT_PICMG)
irq = (irq + 33 - slot) % 4;
else
irq = (irq + 3 + slot) % 4;
}
irq++; /* 1-4 */
switch (irq) {
case 1:
irq = RBTX4938_IRQ_IOC_PCIA;
break;
case 2:
irq = RBTX4938_IRQ_IOC_PCIB;
break;
case 3:
irq = RBTX4938_IRQ_IOC_PCIC;
break;
case 4:
irq = RBTX4938_IRQ_IOC_PCID;
break;
}
return irq;
}
arch/mips/txx9/Kconfig
View file @ 21d638ef
......@@ -39,14 +39,6 @@ config TOSHIBA_RBTX4927
This Toshiba board is based on the TX4927 processor. Say Y here to
support this machine type
config TOSHIBA_RBTX4938
bool "Toshiba RBTX4938 board"
depends on MACH_TX49XX
select SOC_TX4938
help
This Toshiba board is based on the TX4938 processor. Say Y here to
support this machine type
config TOSHIBA_RBTX4939
bool "Toshiba RBTX4939 board"
depends on MACH_TX49XX
......@@ -105,25 +97,5 @@ config PICMG_PCI_BACKPLANE_DEFAULT
depends on PCI && MACH_TXX9
default y if !TOSHIBA_FPCIB0
if TOSHIBA_RBTX4938
comment "Multiplex Pin Select"
choice
prompt "PIO[58:61]"
default TOSHIBA_RBTX4938_MPLEX_PIO58_61
config TOSHIBA_RBTX4938_MPLEX_PIO58_61
bool "PIO"
config TOSHIBA_RBTX4938_MPLEX_NAND
bool "NAND"
config TOSHIBA_RBTX4938_MPLEX_ATA
bool "ATA"
config TOSHIBA_RBTX4938_MPLEX_KEEP
bool "Keep firmware settings"
endchoice
endif
config PCI_TX4927
bool
arch/mips/txx9/Makefile
View file @ 21d638ef
......@@ -14,5 +14,4 @@ obj-$(CONFIG_TOSHIBA_JMR3927) += jmr3927/
# Toshiba RBTX49XX boards
#
obj-$(CONFIG_TOSHIBA_RBTX4927) += rbtx4927/
obj-$(CONFIG_TOSHIBA_RBTX4938) += rbtx4938/
obj-$(CONFIG_TOSHIBA_RBTX4939) += rbtx4939/
arch/mips/txx9/generic/Makefile
View file @ 21d638ef
......@@ -10,5 +10,4 @@ obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o
obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
obj-$(CONFIG_SOC_TX4939) += setup_tx4939.o irq_tx4939.o
obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
obj-$(CONFIG_SPI) += spi_eeprom.o
obj-$(CONFIG_TXX9_7SEGLED) += 7segled.o
arch/mips/txx9/generic/setup.c
View file @ 21d638ef
......@@ -315,11 +315,6 @@ static void __init select_board(void)
txx9_board_vec = &rbtx4937_vec;
break;
#endif
#ifdef CONFIG_TOSHIBA_RBTX4938
case 0x4938:
txx9_board_vec = &rbtx4938_vec;
break;
#endif
#ifdef CONFIG_TOSHIBA_RBTX4939
case 0x4939:
txx9_board_vec = &rbtx4939_vec;
......
arch/mips/txx9/generic/spi_eeprom.c deleted 100644 → 0
View file @ f2c6c22f
/*
* spi_eeprom.c
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <linux/device.h>
#include <linux/spi/spi.h>
#include <linux/spi/eeprom.h>
#include <asm/txx9/spi.h>
#define AT250X0_PAGE_SIZE 8
/* register board information for at25 driver */
int __init spi_eeprom_register(int busid, int chipid, int size)
{
struct spi_board_info info = {
.modalias = "at25",
.max_speed_hz = 1500000, /* 1.5Mbps */
.bus_num = busid,
.chip_select = chipid,
/* Mode 0: High-Active, Sample-Then-Shift */
};
struct spi_eeprom *eeprom;
eeprom = kzalloc(sizeof(*eeprom), GFP_KERNEL);
if (!eeprom)
return -ENOMEM;
strcpy(eeprom->name, "at250x0");
eeprom->byte_len = size;
eeprom->page_size = AT250X0_PAGE_SIZE;
eeprom->flags = EE_ADDR1;
info.platform_data = eeprom;
return spi_register_board_info(&info, 1);
}
/* simple temporary spi driver to provide early access to seeprom. */
static struct read_param {
int busid;
int chipid;
int address;
unsigned char *buf;
int len;
} *read_param;
static int __init early_seeprom_probe(struct spi_device *spi)
{
int stat = 0;
u8 cmd[2];
int len = read_param->len;
char *buf = read_param->buf;
int address = read_param->address;
dev_info(&spi->dev, "spiclk %u KHz.\n",
(spi->max_speed_hz + 500) / 1000);
if (read_param->busid != spi->master->bus_num ||
read_param->chipid != spi->chip_select)
return -ENODEV;
while (len > 0) {
/* spi_write_then_read can only work with small chunk */
int c = len < AT250X0_PAGE_SIZE ? len : AT250X0_PAGE_SIZE;
cmd[0] = 0x03; /* AT25_READ */
cmd[1] = address;
stat = spi_write_then_read(spi, cmd, sizeof(cmd), buf, c);
buf += c;
len -= c;
address += c;
}
return stat;
}
static struct spi_driver early_seeprom_driver __initdata = {
.driver = {
.name = "at25",
},
.probe = early_seeprom_probe,
};
int __init spi_eeprom_read(int busid, int chipid, int address,
unsigned char *buf, int len)
{
int ret;
struct read_param param = {
.busid = busid,
.chipid = chipid,
.address = address,
.buf = buf,
.len = len
};
read_param = &param;
ret = spi_register_driver(&early_seeprom_driver);
if (!ret)
spi_unregister_driver(&early_seeprom_driver);
return ret;
}
arch/mips/txx9/rbtx4938/Makefile deleted 100644 → 0
View file @ f2c6c22f
# SPDX-License-Identifier: GPL-2.0-only
obj-y += prom.o setup.o irq.o
arch/mips/txx9/rbtx4938/irq.c deleted 100644 → 0
View file @ f2c6c22f
/*
* Toshiba RBTX4938 specific interrupt handlers
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
/*
* MIPS_CPU_IRQ_BASE+00 Software 0
* MIPS_CPU_IRQ_BASE+01 Software 1
* MIPS_CPU_IRQ_BASE+02 Cascade TX4938-CP0
* MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use
* MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use
* MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use
* MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use
* MIPS_CPU_IRQ_BASE+07 CPU TIMER
*
* TXX9_IRQ_BASE+00
* TXX9_IRQ_BASE+01
* TXX9_IRQ_BASE+02 Cascade RBTX4938-IOC
* TXX9_IRQ_BASE+03 RBTX4938 RTL-8019AS Ethernet
* TXX9_IRQ_BASE+04
* TXX9_IRQ_BASE+05 TX4938 ETH1
* TXX9_IRQ_BASE+06 TX4938 ETH0
* TXX9_IRQ_BASE+07
* TXX9_IRQ_BASE+08 TX4938 SIO 0
* TXX9_IRQ_BASE+09 TX4938 SIO 1
* TXX9_IRQ_BASE+10 TX4938 DMA0
* TXX9_IRQ_BASE+11 TX4938 DMA1
* TXX9_IRQ_BASE+12 TX4938 DMA2
* TXX9_IRQ_BASE+13 TX4938 DMA3
* TXX9_IRQ_BASE+14
* TXX9_IRQ_BASE+15
* TXX9_IRQ_BASE+16 TX4938 PCIC
* TXX9_IRQ_BASE+17 TX4938 TMR0
* TXX9_IRQ_BASE+18 TX4938 TMR1
* TXX9_IRQ_BASE+19 TX4938 TMR2
* TXX9_IRQ_BASE+20
* TXX9_IRQ_BASE+21
* TXX9_IRQ_BASE+22 TX4938 PCIERR
* TXX9_IRQ_BASE+23
* TXX9_IRQ_BASE+24
* TXX9_IRQ_BASE+25
* TXX9_IRQ_BASE+26
* TXX9_IRQ_BASE+27
* TXX9_IRQ_BASE+28
* TXX9_IRQ_BASE+29
* TXX9_IRQ_BASE+30
* TXX9_IRQ_BASE+31 TX4938 SPI
*
* RBTX4938_IRQ_IOC+00 PCI-D
* RBTX4938_IRQ_IOC+01 PCI-C
* RBTX4938_IRQ_IOC+02 PCI-B
* RBTX4938_IRQ_IOC+03 PCI-A
* RBTX4938_IRQ_IOC+04 RTC
* RBTX4938_IRQ_IOC+05 ATA
* RBTX4938_IRQ_IOC+06 MODEM
* RBTX4938_IRQ_IOC+07 SWINT
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/mipsregs.h>
#include <asm/txx9/generic.h>
#include <asm/txx9/rbtx4938.h>
static int toshiba_rbtx4938_irq_nested(int sw_irq)
{
u8 level3;
level3 = readb(rbtx4938_imstat_addr);
if (unlikely(!level3))
return -1;
/* must use fls so onboard ATA has priority */
return RBTX4938_IRQ_IOC + __fls8(level3);
}
static void toshiba_rbtx4938_irq_ioc_enable(struct irq_data *d)
{
unsigned char v;
v = readb(rbtx4938_imask_addr);
v |= (1 << (d->irq - RBTX4938_IRQ_IOC));
writeb(v, rbtx4938_imask_addr);
mmiowb();
}
static void toshiba_rbtx4938_irq_ioc_disable(struct irq_data *d)
{
unsigned char v;
v = readb(rbtx4938_imask_addr);
v &= ~(1 << (d->irq - RBTX4938_IRQ_IOC));
writeb(v, rbtx4938_imask_addr);
mmiowb();
}
#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
.name = TOSHIBA_RBTX4938_IOC_NAME,
.irq_mask = toshiba_rbtx4938_irq_ioc_disable,
.irq_unmask = toshiba_rbtx4938_irq_ioc_enable,
};
static int rbtx4938_irq_dispatch(int pending)
{
int irq;
if (pending & STATUSF_IP7)
irq = MIPS_CPU_IRQ_BASE + 7;
else if (pending & STATUSF_IP2) {
irq = txx9_irq();
if (irq == RBTX4938_IRQ_IOCINT)
irq = toshiba_rbtx4938_irq_nested(irq);
} else if (pending & STATUSF_IP1)
irq = MIPS_CPU_IRQ_BASE + 0;
else if (pending & STATUSF_IP0)
irq = MIPS_CPU_IRQ_BASE + 1;
else
irq = -1;
return irq;
}
static void __init toshiba_rbtx4938_irq_ioc_init(void)
{
int i;
for (i = RBTX4938_IRQ_IOC;
i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
irq_set_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
handle_level_irq);
irq_set_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
}
void __init rbtx4938_irq_setup(void)
{
txx9_irq_dispatch = rbtx4938_irq_dispatch;
/* Now, interrupt control disabled, */
/* all IRC interrupts are masked, */
/* all IRC interrupt mode are Low Active. */
/* mask all IOC interrupts */
writeb(0, rbtx4938_imask_addr);
/* clear SoftInt interrupts */
writeb(0, rbtx4938_softint_addr);
tx4938_irq_init();
toshiba_rbtx4938_irq_ioc_init();
/* Onboard 10M Ether: High Active */
irq_set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
}
arch/mips/txx9/rbtx4938/prom.c deleted 100644 → 0
View file @ f2c6c22f
/*
* rbtx4938 specific prom routines
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#include <linux/init.h>
#include <linux/memblock.h>
#include <asm/txx9/generic.h>
#include <asm/txx9/rbtx4938.h>
void __init rbtx4938_prom_init(void)
{
memblock_add(0, tx4938_get_mem_size());
txx9_sio_putchar_init(TX4938_SIO_REG(0) & 0xfffffffffULL);
}
arch/mips/txx9/rbtx4938/setup.c deleted 100644 → 0
View file @ f2c6c22f
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