Commit 21e4b072 authored by Larry Finger's avatar Larry Finger Committed by John W. Linville

rtlwifi: rtl8821ae: Move driver from staging to regular tree

This driver was entered into staging a few cycles ago because there was
not time to integrate the Realtek version into the support routines in
the kernel. Now that there is an effort to converg the code base from Linux
and the Realtek repo, it is time to move this driver. In addition, all the
updates included in the 06/28/2014 version of the Realtek drivers are
included here.

With this change, it will be necessary to delete the staging driver. That
will be handled in a separate patch. As it impacts the staging tree, such a
patch is sent to a different destination.
Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent c151aed6
......@@ -5,7 +5,7 @@ menuconfig RTL_CARDS
---help---
This option will enable support for the Realtek mac80211-based
wireless drivers. Drivers rtl8192ce, rtl8192cu, rtl8192se, rtl8192de,
rtl8723ae, rtl8723be, and rtl8188ae share some common code.
rtl8723ae, rtl8723be, rtl8188ee, and rtl8821ae share some common code.
if RTL_CARDS
......@@ -80,6 +80,17 @@ config RTL8188EE
If you choose to build it as a module, it will be called rtl8188ee
config RTL8821AE
tristate "Realtek RTL8821AE/RTL8812AE Wireless Network Adapter"
depends on PCI
select RTLWIFI
select RTLWIFI_PCI
---help---
This is the driver for Realtek RTL8i821AE/RTL8812AE 802.11av PCIe
wireless network adapters.
If you choose to build it as a module, it will be called rtl8821ae
config RTL8192CU
tristate "Realtek RTL8192CU/RTL8188CU USB Wireless Network Adapter"
depends on USB
......
......@@ -28,5 +28,6 @@ obj-$(CONFIG_RTL8723BE) += rtl8723be/
obj-$(CONFIG_RTL8188EE) += rtl8188ee/
obj-$(CONFIG_RTLBTCOEXIST) += btcoexist/
obj-$(CONFIG_RTL8723_COMMON) += rtl8723com/
obj-$(CONFIG_RTL8821AE) += rtl8821ae/
ccflags-y += -D__CHECK_ENDIAN__
......@@ -104,6 +104,7 @@
#define COMP_USB BIT(29)
#define COMP_EASY_CONCURRENT COMP_USB /* reuse of this bit is OK */
#define COMP_BT_COEXIST BIT(30)
#define COMP_IQK BIT(31)
/*--------------------------------------------------------------
Define the rt_print components
......
/******************************************************************************
*
* Copyright(c) 2009-2012 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8723E_PWRSEQCMD_H__
#define __RTL8723E_PWRSEQCMD_H__
#include "wifi.h"
/*---------------------------------------------
* 3 The value of cmd: 4 bits
*---------------------------------------------
*/
#define PWR_CMD_READ 0x00
#define PWR_CMD_WRITE 0x01
#define PWR_CMD_POLLING 0x02
#define PWR_CMD_DELAY 0x03
#define PWR_CMD_END 0x04
/* define the base address of each block */
#define PWR_BASEADDR_MAC 0x00
#define PWR_BASEADDR_USB 0x01
#define PWR_BASEADDR_PCIE 0x02
#define PWR_BASEADDR_SDIO 0x03
#define PWR_INTF_SDIO_MSK BIT(0)
#define PWR_INTF_USB_MSK BIT(1)
#define PWR_INTF_PCI_MSK BIT(2)
#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
#define PWR_FAB_TSMC_MSK BIT(0)
#define PWR_FAB_UMC_MSK BIT(1)
#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
#define PWR_CUT_TESTCHIP_MSK BIT(0)
#define PWR_CUT_A_MSK BIT(1)
#define PWR_CUT_B_MSK BIT(2)
#define PWR_CUT_C_MSK BIT(3)
#define PWR_CUT_D_MSK BIT(4)
#define PWR_CUT_E_MSK BIT(5)
#define PWR_CUT_F_MSK BIT(6)
#define PWR_CUT_G_MSK BIT(7)
#define PWR_CUT_ALL_MSK 0xFF
enum pwrseq_delay_unit {
PWRSEQ_DELAY_US,
PWRSEQ_DELAY_MS,
};
struct wlan_pwr_cfg {
u16 offset;
u8 cut_msk;
u8 fab_msk:4;
u8 interface_msk:4;
u8 base:4;
u8 cmd:4;
u8 msk;
u8 value;
};
#define GET_PWR_CFG_OFFSET(__PWR_CMD) (__PWR_CMD.offset)
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) (__PWR_CMD.cut_msk)
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) (__PWR_CMD.fab_msk)
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) (__PWR_CMD.interface_msk)
#define GET_PWR_CFG_BASE(__PWR_CMD) (__PWR_CMD.base)
#define GET_PWR_CFG_CMD(__PWR_CMD) (__PWR_CMD.cmd)
#define GET_PWR_CFG_MASK(__PWR_CMD) (__PWR_CMD.msk)
#define GET_PWR_CFG_VALUE(__PWR_CMD) (__PWR_CMD.value)
bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
u8 fab_version, u8 interface_type,
struct wlan_pwr_cfg pwrcfgcmd[]);
#endif
obj-m := rtl8821ae.o
rtl8821ae-objs := \
dm.o \
fw.o \
hw.o \
led.o \
phy.o \
pwrseq.o \
rf.o \
sw.o \
table.o \
trx.o \
obj-$(CONFIG_RTL8821AE) += rtl8821ae.o
ccflags-y += -D__CHECK_ENDIAN__
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_HW_H__
#define __RTL8821AE_HW_H__
void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw);
void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
u32 *p_inta, u32 *p_intb);
int rtl8821ae_hw_init(struct ieee80211_hw *hw);
void rtl8821ae_card_disable(struct ieee80211_hw *hw);
void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw);
void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw);
int rtl8821ae_set_network_type(struct ieee80211_hw *hw,
enum nl80211_iftype type);
void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci);
void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw);
void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw);
void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
u32 add_msr, u32 rm_msr);
void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
struct ieee80211_sta *sta,
u8 rssi_level);
void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw);
bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw);
void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
u8 *p_macaddr, bool is_group, u8 enc_algo,
bool is_wepkey, bool clear_all);
void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw);
void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw);
void rtl8821ae_suspend(struct ieee80211_hw *hw);
void rtl8821ae_resume(struct ieee80211_hw *hw);
void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
bool allow_all_da,
bool write_into_reg);
void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw);
void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw);
void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
struct rtl_wow_pattern *rtl_pattern,
u8 index);
#endif
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../wifi.h"
#include "../pci.h"
#include "reg.h"
#include "led.h"
static void _rtl8821ae_init_led(struct ieee80211_hw *hw,
struct rtl_led *pled,
enum rtl_led_pin ledpin)
{
pled->hw = hw;
pled->ledpin = ledpin;
pled->ledon = false;
}
void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
{
u8 ledcfg;
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
"LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
switch (pled->ledpin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
ledcfg &= ~BIT(6);
rtl_write_byte(rtlpriv,
REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5));
break;
case LED_PIN_LED1:
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg & 0x10);
break;
default:
RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
"switch case not process\n");
break;
}
pled->ledon = true;
}
void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
{
u16 ledreg = REG_LEDCFG1;
u8 ledcfg = 0;
struct rtl_priv *rtlpriv = rtl_priv(hw);
switch (pled->ledpin) {
case LED_PIN_LED0:
ledreg = REG_LEDCFG1;
break;
case LED_PIN_LED1:
ledreg = REG_LEDCFG2;
break;
case LED_PIN_GPIO0:
default:
break;
}
RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
"In SwLedOn, LedAddr:%X LEDPIN=%d\n",
ledreg, pled->ledpin);
ledcfg = rtl_read_byte(rtlpriv, ledreg);
ledcfg |= BIT(5); /*Set 0x4c[21]*/
ledcfg &= ~(BIT(7) | BIT(6) | BIT(3) | BIT(2) | BIT(1) | BIT(0));
/*Clear 0x4c[23:22] and 0x4c[19:16]*/
rtl_write_byte(rtlpriv, ledreg, ledcfg); /*SW control led0 on.*/
pled->ledon = true;
}
void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
u8 ledcfg;
RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
"LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
switch (pled->ledpin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
ledcfg &= 0xf0;
if (pcipriv->ledctl.led_opendrain) {
ledcfg &= 0x90; /* Set to software control. */
rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg|BIT(3)));
ledcfg = rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG);
ledcfg &= 0xFE;
rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, ledcfg);
} else {
ledcfg &= ~BIT(6);
rtl_write_byte(rtlpriv, REG_LEDCFG2,
(ledcfg | BIT(3) | BIT(5)));
}
break;
case LED_PIN_LED1:
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
ledcfg &= 0x10; /* Set to software control. */
rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg|BIT(3));
break;
default:
RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
"switch case not process\n");
break;
}
pled->ledon = false;
}
void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
{
u16 ledreg = REG_LEDCFG1;
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
switch (pled->ledpin) {
case LED_PIN_LED0:
ledreg = REG_LEDCFG1;
break;
case LED_PIN_LED1:
ledreg = REG_LEDCFG2;
break;
case LED_PIN_GPIO0:
default:
break;
}
RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
"In SwLedOff,LedAddr:%X LEDPIN=%d\n",
ledreg, pled->ledpin);
/*Open-drain arrangement for controlling the LED*/
if (pcipriv->ledctl.led_opendrain) {
u8 ledcfg = rtl_read_byte(rtlpriv, ledreg);
ledreg &= 0xd0; /* Set to software control.*/
rtl_write_byte(rtlpriv, ledreg, (ledcfg | BIT(3)));
/*Open-drain arrangement*/
ledcfg = rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG);
ledcfg &= 0xFE;/*Set GPIO[8] to input mode*/
rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, ledcfg);
} else {
rtl_write_byte(rtlpriv, ledreg, 0x28);
}
pled->ledon = false;
}
void rtl8821ae_init_sw_leds(struct ieee80211_hw *hw)
{
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
_rtl8821ae_init_led(hw, &pcipriv->ledctl.sw_led0, LED_PIN_LED0);
_rtl8821ae_init_led(hw, &pcipriv->ledctl.sw_led1, LED_PIN_LED1);
}
static void _rtl8821ae_sw_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
struct rtl_led *pLed0 = &pcipriv->ledctl.sw_led0;
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
switch (ledaction) {
case LED_CTL_POWER_ON:
case LED_CTL_LINK:
case LED_CTL_NO_LINK:
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
rtl8812ae_sw_led_on(hw, pLed0);
else
rtl8821ae_sw_led_on(hw, pLed0);
break;
case LED_CTL_POWER_OFF:
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
rtl8812ae_sw_led_off(hw, pLed0);
else
rtl8821ae_sw_led_off(hw, pLed0);
break;
default:
break;
}
}
void rtl8821ae_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
if ((ppsc->rfoff_reason > RF_CHANGE_BY_PS) &&
(ledaction == LED_CTL_TX ||
ledaction == LED_CTL_RX ||
ledaction == LED_CTL_SITE_SURVEY ||
ledaction == LED_CTL_LINK ||
ledaction == LED_CTL_NO_LINK ||
ledaction == LED_CTL_START_TO_LINK ||
ledaction == LED_CTL_POWER_ON)) {
return;
}
RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, "ledaction %d,\n",
ledaction);
_rtl8821ae_sw_led_control(hw, ledaction);
}
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_LED_H__
#define __RTL8821AE_LED_H__
void rtl8821ae_init_sw_leds(struct ieee80211_hw *hw);
void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
void rtl8821ae_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction);
#endif
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_PHY_H__
#define __RTL8821AE_PHY_H__
/* MAX_TX_COUNT must always be set to 4, otherwise read
* efuse table sequence will be wrong.
*/
#define MAX_TX_COUNT 4
#define TX_1S 0
#define TX_2S 1
#define TX_3S 2
#define TX_4S 3
#define MAX_POWER_INDEX 0x3F
#define MAX_PRECMD_CNT 16
#define MAX_RFDEPENDCMD_CNT 16
#define MAX_POSTCMD_CNT 16
#define MAX_DOZE_WAITING_TIMES_9x 64
#define RT_CANNOT_IO(hw) false
#define HIGHPOWER_RADIOA_ARRAYLEN 22
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM 9
#define MAX_TOLERANCE 5
#define IQK_DELAY_TIME 10
#define index_mapping_NUM 15
#define APK_BB_REG_NUM 5
#define APK_AFE_REG_NUM 16
#define APK_CURVE_REG_NUM 4
#define PATH_NUM 2
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50
#define AntennaDiversityValue 0x80
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#define IQK_ADDA_REG_NUM 16
#define IQK_MAC_REG_NUM 4
#define RF6052_MAX_PATH 2
#define CT_OFFSET_MAC_ADDR 0X16
#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
#define CT_OFFSET_CHANNEL_PLAH 0x75
#define CT_OFFSET_THERMAL_METER 0x78
#define CT_OFFSET_RF_OPTION 0x79
#define CT_OFFSET_VERSION 0x7E
#define CT_OFFSET_CUSTOMER_ID 0x7F
#define RTL8821AE_MAX_PATH_NUM 2
#define TARGET_CHNL_NUM_2G_5G_8812 59
enum swchnlcmd_id {
CMDID_END,
CMDID_SET_TXPOWEROWER_LEVEL,
CMDID_BBREGWRITE10,
CMDID_WRITEPORT_ULONG,
CMDID_WRITEPORT_USHORT,
CMDID_WRITEPORT_UCHAR,
CMDID_RF_WRITEREG,
};
struct swchnlcmd {
enum swchnlcmd_id cmdid;
u32 para1;
u32 para2;
u32 msdelay;
};
enum hw90_block_e {
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4,
};
enum baseband_config_type {
BASEBAND_CONFIG_PHY_REG = 0,
BASEBAND_CONFIG_AGC_TAB = 1,
};
enum ra_offset_area {
RA_OFFSET_LEGACY_OFDM1,
RA_OFFSET_LEGACY_OFDM2,
RA_OFFSET_HT_OFDM1,
RA_OFFSET_HT_OFDM2,
RA_OFFSET_HT_OFDM3,
RA_OFFSET_HT_OFDM4,
RA_OFFSET_HT_CCK,
};
enum antenna_path {
ANTENNA_NONE,
ANTENNA_D,
ANTENNA_C,
ANTENNA_CD,
ANTENNA_B,
ANTENNA_BD,
ANTENNA_BC,
ANTENNA_BCD,
ANTENNA_A,
ANTENNA_AD,
ANTENNA_AC,
ANTENNA_ACD,
ANTENNA_AB,
ANTENNA_ABD,
ANTENNA_ABC,
ANTENNA_ABCD
};
struct r_antenna_select_ofdm {
u32 r_tx_antenna:4;
u32 r_ant_l:4;
u32 r_ant_non_ht:4;
u32 r_ant_ht1:4;
u32 r_ant_ht2:4;
u32 r_ant_ht_s1:4;
u32 r_ant_non_ht_s1:4;
u32 ofdm_txsc:2;
u32 reserved:2;
};
struct r_antenna_select_cck {
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable:2;
u8 r_ccktx_enable:4;
};
struct efuse_contents {
u8 mac_addr[ETH_ALEN];
u8 cck_tx_power_idx[6];
u8 ht40_1s_tx_power_idx[6];
u8 ht40_2s_tx_power_idx_diff[3];
u8 ht20_tx_power_idx_diff[3];
u8 ofdm_tx_power_idx_diff[3];
u8 ht40_max_power_offset[3];
u8 ht20_max_power_offset[3];
u8 channel_plan;
u8 thermal_meter;
u8 rf_option[5];
u8 version;
u8 oem_id;
u8 regulatory;
};
struct tx_power_struct {
u8 cck[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
u8 ht40_1s[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
u8 ht40_2s[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
u8 ht20_diff[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
u8 legacy_ht_diff[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
u8 legacy_ht_txpowerdiff;
u8 groupht20[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
u8 groupht40[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
u8 pwrgroup_cnt;
u32 mcs_original_offset[4][16];
};
enum _ANT_DIV_TYPE {
NO_ANTDIV = 0xFF,
CG_TRX_HW_ANTDIV = 0x01,
CGCS_RX_HW_ANTDIV = 0x02,
FIXED_HW_ANTDIV = 0x03,
CG_TRX_SMART_ANTDIV = 0x04,
CGCS_RX_SW_ANTDIV = 0x05,
};
u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw,
u32 regaddr, u32 bitmask);
void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw,
u32 regaddr, u32 bitmask, u32 data);
u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw,
enum radio_path rfpath, u32 regaddr,
u32 bitmask);
void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw,
enum radio_path rfpath, u32 regaddr,
u32 bitmask, u32 data);
bool rtl8821ae_phy_mac_config(struct ieee80211_hw *hw);
bool rtl8821ae_phy_bb_config(struct ieee80211_hw *hw);
bool rtl8821ae_phy_rf_config(struct ieee80211_hw *hw);
void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw *hw,
u8 band);
void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw *hw,
long *powerlevel);
void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw *hw,
u8 channel);
void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw *hw,
u8 operation);
void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw *hw,
enum nl80211_channel_type ch_type);
void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw *hw);
u8 rtl8821ae_phy_sw_chnl(struct ieee80211_hw *hw);
void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw,
bool b_recovery);
void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw *hw,
bool b_recovery);
void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw);
void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
enum radio_path rfpath);
bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
enum radio_path rfpath);
bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
enum rf_pwrstate rfpwr_state);
u8 _rtl8812ae_get_right_chnl_place_for_iqk(u8 chnl);
void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
u8 channel, u8 path);
void rtl8812ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
u8 thermal_value, u8 threshold);
void rtl8821ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
u8 thermal_value, u8 threshold);
void rtl8821ae_reset_iqk_result(struct ieee80211_hw *hw);
u32 phy_get_tx_swing_8812A(struct ieee80211_hw *hw, u8 band, u8 rf_path);
#endif
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../pwrseqcmd.h"
#include "pwrseq.h"
/* drivers should parse below arrays and do the corresponding actions */
/* 3 Power on Array */
struct wlan_pwr_cfg rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS +
RTL8812_TRANS_END_STEPS] = {
RTL8812_TRANS_CARDEMU_TO_ACT
RTL8812_TRANS_END
};
/* 3Radio off GPIO Array */
struct wlan_pwr_cfg rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8812_TRANS_END_STEPS] = {
RTL8812_TRANS_ACT_TO_CARDEMU
RTL8812_TRANS_END
};
/* 3Card Disable Array */
struct wlan_pwr_cfg rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8812_TRANS_CARDEMU_TO_PDN_STEPS
+ RTL8812_TRANS_END_STEPS] = {
RTL8812_TRANS_ACT_TO_CARDEMU
RTL8812_TRANS_CARDEMU_TO_CARDDIS
RTL8812_TRANS_END
};
/* 3 Card Enable Array */
struct wlan_pwr_cfg rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8812_TRANS_CARDEMU_TO_PDN_STEPS
+ RTL8812_TRANS_END_STEPS] = {
RTL8812_TRANS_CARDDIS_TO_CARDEMU
RTL8812_TRANS_CARDEMU_TO_ACT
RTL8812_TRANS_END
};
/* 3Suspend Array */
struct wlan_pwr_cfg rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8812_TRANS_CARDEMU_TO_SUS_STEPS +
RTL8812_TRANS_END_STEPS] = {
RTL8812_TRANS_ACT_TO_CARDEMU
RTL8812_TRANS_CARDEMU_TO_SUS
RTL8812_TRANS_END
};
/* 3 Resume Array */
struct wlan_pwr_cfg rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8812_TRANS_CARDEMU_TO_SUS_STEPS +
RTL8812_TRANS_END_STEPS] = {
RTL8812_TRANS_SUS_TO_CARDEMU
RTL8812_TRANS_CARDEMU_TO_ACT
RTL8812_TRANS_END
};
/* 3HWPDN Array */
struct wlan_pwr_cfg rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8812_TRANS_END_STEPS] = {
RTL8812_TRANS_ACT_TO_CARDEMU
RTL8812_TRANS_CARDEMU_TO_PDN
RTL8812_TRANS_END
};
/* 3 Enter LPS */
struct wlan_pwr_cfg rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS +
RTL8812_TRANS_END_STEPS] = {
/* FW behavior */
RTL8812_TRANS_ACT_TO_LPS
RTL8812_TRANS_END
};
/* 3 Leave LPS */
struct wlan_pwr_cfg rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS +
RTL8812_TRANS_END_STEPS] = {
/* FW behavior */
RTL8812_TRANS_LPS_TO_ACT
RTL8812_TRANS_END
};
/* drivers should parse below arrays and do the corresponding actions */
/*3 Power on Array*/
struct wlan_pwr_cfg rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS
+ RTL8821A_TRANS_END_STEPS] = {
RTL8821A_TRANS_CARDEMU_TO_ACT
RTL8821A_TRANS_END
};
/*3Radio off GPIO Array */
struct wlan_pwr_cfg rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_END_STEPS] = {
RTL8821A_TRANS_ACT_TO_CARDEMU
RTL8821A_TRANS_END
};
/*3Card Disable Array*/
struct wlan_pwr_cfg rtl8821A_card_disable_flow
[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS
+ RTL8821A_TRANS_END_STEPS] = {
RTL8821A_TRANS_ACT_TO_CARDEMU
RTL8821A_TRANS_CARDEMU_TO_CARDDIS
RTL8821A_TRANS_END
};
/*3 Card Enable Array*/
/*RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS*/
struct wlan_pwr_cfg rtl8821A_card_enable_flow
[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS
+ RTL8821A_TRANS_END_STEPS] = {
RTL8821A_TRANS_CARDDIS_TO_CARDEMU
RTL8821A_TRANS_CARDEMU_TO_ACT
RTL8821A_TRANS_END
};
/*3Suspend Array*/
struct wlan_pwr_cfg rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS
+ RTL8821A_TRANS_END_STEPS] = {
RTL8821A_TRANS_ACT_TO_CARDEMU
RTL8821A_TRANS_CARDEMU_TO_SUS
RTL8821A_TRANS_END
};
/*3 Resume Array*/
struct wlan_pwr_cfg rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS
+ RTL8821A_TRANS_END_STEPS] = {
RTL8821A_TRANS_SUS_TO_CARDEMU
RTL8821A_TRANS_CARDEMU_TO_ACT
RTL8821A_TRANS_END
};
/*3HWPDN Array*/
struct wlan_pwr_cfg rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS
+ RTL8821A_TRANS_END_STEPS] = {
RTL8821A_TRANS_ACT_TO_CARDEMU
RTL8821A_TRANS_CARDEMU_TO_PDN
RTL8821A_TRANS_END
};
/*3 Enter LPS */
struct wlan_pwr_cfg rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS
+ RTL8821A_TRANS_END_STEPS] = {
/*FW behavior*/
RTL8821A_TRANS_ACT_TO_LPS
RTL8821A_TRANS_END
};
/*3 Leave LPS */
struct wlan_pwr_cfg rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS
+ RTL8821A_TRANS_END_STEPS] = {
/*FW behavior*/
RTL8821A_TRANS_LPS_TO_ACT
RTL8821A_TRANS_END
};
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_RF_H__
#define __RTL8821AE_RF_H__
#define RF6052_MAX_TX_PWR 0x3F
#define RF6052_MAX_REG 0x3F
void rtl8821ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
u8 bandwidth);
void rtl8821ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
u8 *ppowerlevel);
void rtl8821ae_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
u8 *ppowerlevel_ofdm,
u8 *ppowerlevel_bw20,
u8 *ppowerlevel_bw40,
u8 channel);
bool rtl8821ae_phy_rf6052_config(struct ieee80211_hw *hw);
#endif
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_SW_H__
#define __RTL8821AE_SW_H__
int rtl8821ae_init_sw_vars(struct ieee80211_hw *hw);
void rtl8821ae_deinit_sw_vars(struct ieee80211_hw *hw);
void rtl8821ae_init_var_map(struct ieee80211_hw *hw);
bool rtl8821ae_get_btc_status(void);
#endif
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Created on 2010/ 5/18, 1:41
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_TABLE__H_
#define __RTL8821AE_TABLE__H_
#include <linux/types.h>
#define RTL8821AEPHY_REG_1TARRAYLEN 344
extern u32 RTL8821AE_PHY_REG_ARRAY[];
#define RTL8812AEPHY_REG_1TARRAYLEN 490
extern u32 RTL8812AE_PHY_REG_ARRAY[];
#define RTL8821AEPHY_REG_ARRAY_PGLEN 90
extern u32 RTL8821AE_PHY_REG_ARRAY_PG[];
#define RTL8812AEPHY_REG_ARRAY_PGLEN 276
extern u32 RTL8812AE_PHY_REG_ARRAY_PG[];
/* #define RTL8723BE_RADIOA_1TARRAYLEN 206 */
/* extern u8 *RTL8821AE_TXPWR_LMT_ARRAY[]; */
#define RTL8812AE_RADIOA_1TARRAYLEN 1264
extern u32 RTL8812AE_RADIOA_ARRAY[];
#define RTL8812AE_RADIOB_1TARRAYLEN 1240
extern u32 RTL8812AE_RADIOB_ARRAY[];
#define RTL8821AE_RADIOA_1TARRAYLEN 1176
extern u32 RTL8821AE_RADIOA_ARRAY[];
#define RTL8821AEMAC_1T_ARRAYLEN 194
extern u32 RTL8821AE_MAC_REG_ARRAY[];
#define RTL8812AEMAC_1T_ARRAYLEN 214
extern u32 RTL8812AE_MAC_REG_ARRAY[];
#define RTL8821AEAGCTAB_1TARRAYLEN 382
extern u32 RTL8821AE_AGC_TAB_ARRAY[];
#define RTL8812AEAGCTAB_1TARRAYLEN 1312
extern u32 RTL8812AE_AGC_TAB_ARRAY[];
#define RTL8812AE_TXPWR_LMT_ARRAY_LEN 3948
extern u8 *RTL8812AE_TXPWR_LMT[];
#define RTL8821AE_TXPWR_LMT_ARRAY_LEN 3948
extern u8 *RTL8821AE_TXPWR_LMT[];
#endif
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