Commit 21e871fe authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman

staging: comedi: mite: cleanup remaining mite register/bits

For aesthetics, convert the register/bit enums into defines and
use the BIT() macro to define the bits.
Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 7024cc88
...@@ -104,49 +104,49 @@ int mite_init_ring_descriptors(struct mite_dma_descriptor_ring *ring, ...@@ -104,49 +104,49 @@ int mite_init_ring_descriptors(struct mite_dma_descriptor_ring *ring,
struct comedi_subdevice *s, struct comedi_subdevice *s,
unsigned int nbytes); unsigned int nbytes);
enum mite_registers { /*
MITE_IODWBSR = 0xc0, /* IO Device Window Base Size Register */ * Mite registers (used outside of the mite driver)
MITE_IODWBSR_1 = 0xc4, /* IO Device Window Base Size Register 1 */ */
MITE_IODWCR_1 = 0xf4, #define MITE_IODWBSR 0xc0 /* IO Device Window Base Size */
}; #define MITE_IODWBSR_1 0xc4 /* IO Device Window1 Base Size */
#define WENAB BIT(7) /* window enable */
enum MITE_IODWBSR_bits { #define MITE_IODWCR_1 0xf4
WENAB = 0x80, /* window enable */
}; #define CHSR_INT BIT(31)
#define CHSR_LPAUSES BIT(29)
enum CHSR_bits { #define CHSR_SARS BIT(27)
CHSR_INT = (1 << 31), #define CHSR_DONE BIT(25)
CHSR_LPAUSES = (1 << 29), #define CHSR_MRDY BIT(23)
CHSR_SARS = (1 << 27), #define CHSR_DRDY BIT(21)
CHSR_DONE = (1 << 25), #define CHSR_LINKC BIT(19)
CHSR_MRDY = (1 << 23), #define CHSR_CONTS_RB BIT(17)
CHSR_DRDY = (1 << 21), #define CHSR_ERROR BIT(15)
CHSR_LINKC = (1 << 19), #define CHSR_SABORT BIT(14)
CHSR_CONTS_RB = (1 << 17), #define CHSR_HABORT BIT(13)
CHSR_ERROR = (1 << 15), #define CHSR_STOPS BIT(12)
CHSR_SABORT = (1 << 14), #define CHSR_OPERR(x) (((x) & 0x3) << 10)
CHSR_HABORT = (1 << 13), #define CHSR_OPERR_MASK CHSR_OPERR(3)
CHSR_STOPS = (1 << 12), #define CHSR_OPERR_NOERROR CHSR_OPERR(0)
CHSR_OPERR_MASK = (3 << 10), #define CHSR_OPERR_FIFOERROR CHSR_OPERR(1)
CHSR_OPERR_NOERROR = (0 << 10), #define CHSR_OPERR_LINKERROR CHSR_OPERR(1) /* ??? */
CHSR_OPERR_FIFOERROR = (1 << 10), #define CHSR_XFERR BIT(9)
CHSR_OPERR_LINKERROR = (1 << 10), /* ??? */ #define CHSR_END BIT(8)
CHSR_XFERR = (1 << 9), #define CHSR_DRQ1 BIT(7)
CHSR_END = (1 << 8), #define CHSR_DRQ0 BIT(6)
CHSR_DRQ1 = (1 << 7), #define CHSR_LERR(x) (((x) & 0x3) << 4)
CHSR_DRQ0 = (1 << 6), #define CHSR_LERR_MASK CHSR_LERR(3)
CHSR_LERR_MASK = (3 << 4), #define CHSR_LBERR CHSR_LERR(1)
CHSR_LBERR = (1 << 4), #define CHSR_LRERR CHSR_LERR(2)
CHSR_LRERR = (2 << 4), #define CHSR_LOERR CHSR_LERR(3)
CHSR_LOERR = (3 << 4), #define CHSR_MERR(x) (((x) & 0x3) << 2)
CHSR_MERR_MASK = (3 << 2), #define CHSR_MERR_MASK CHSR_MERR(3)
CHSR_MBERR = (1 << 2), #define CHSR_MBERR CHSR_MERR(1)
CHSR_MRERR = (2 << 2), #define CHSR_MRERR CHSR_MERR(2)
CHSR_MOERR = (3 << 2), #define CHSR_MOERR CHSR_MERR(3)
CHSR_DERR_MASK = (3 << 0), #define CHSR_DERR(x) (((x) & 0x3) << 0)
CHSR_DBERR = (1 << 0), #define CHSR_DERR_MASK CHSR_DERR(3)
CHSR_DRERR = (2 << 0), #define CHSR_DBERR CHSR_DERR(1)
CHSR_DOERR = (3 << 0), #define CHSR_DRERR CHSR_DERR(2)
}; #define CHSR_DOERR CHSR_DERR(3)
#endif #endif
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