Commit 2259918e authored by JinZe.Xu's avatar JinZe.Xu Committed by Alex Deucher

drm/amd/display: Control power gating by driver.

[Why]
This disablement would be specific for Nav10 and shouldn’t be propagated to the other programs.

[How]
Power gating is controlled by driver.
Signed-off-by: default avatarJinZe.Xu <JinZe.Xu@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 346cf627
......@@ -86,17 +86,12 @@ void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool po
1, 1000);
break;
case 4: /* DPP4 */
/*
* Do not power gate DPP4, should be left at HW default, power on permanently.
* PG on Pipe4 is De-featured, attempting to put it to PG state may result in hard
* reset.
* REG_UPDATE(DOMAIN9_PG_CONFIG,
* DOMAIN9_POWER_GATE, power_gate);
*
* REG_WAIT(DOMAIN9_PG_STATUS,
* DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
* 1, 1000);
*/
REG_UPDATE(DOMAIN9_PG_CONFIG,
DOMAIN9_POWER_GATE, power_gate);
REG_WAIT(DOMAIN9_PG_STATUS,
DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
1, 1000);
break;
default:
BREAK_TO_DEBUGGER();
......@@ -148,17 +143,12 @@ void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool
1, 1000);
break;
case 4: /* DCHUBP4 */
/*
* Do not power gate DCHUB4, should be left at HW default, power on permanently.
* PG on Pipe4 is De-featured, attempting to put it to PG state may result in hard
* reset.
* REG_UPDATE(DOMAIN8_PG_CONFIG,
* DOMAIN8_POWER_GATE, power_gate);
*
* REG_WAIT(DOMAIN8_PG_STATUS,
* DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
* 1, 1000);
*/
REG_UPDATE(DOMAIN8_PG_CONFIG,
DOMAIN8_POWER_GATE, power_gate);
REG_WAIT(DOMAIN8_PG_STATUS,
DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
1, 1000);
break;
default:
BREAK_TO_DEBUGGER();
......
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