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Commit 2374b99e authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Bjorn Andersson
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arm64: dts: qcom: align clocks in I2C/SPI with DT schema 

The DT schema expects clocks core-iface order.  No functional change.
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220405063451.12011-3-krzysztof.kozlowski@linaro.org
parent 0e1b27f4
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Showing with 135 additions and 135 deletions
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View file @ 2374b99e
...@@ -318,9 +318,9 @@ i2c_0: i2c@78b6000 { ...@@ -318,9 +318,9 @@ i2c_0: i2c@78b6000 {
#size-cells = <0>; #size-cells = <0>;
reg = <0x0 0x078b6000 0x0 0x600>; reg = <0x0 0x078b6000 0x0 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clock-frequency = <400000>; clock-frequency = <400000>;
dmas = <&blsp_dma 14>, <&blsp_dma 15>; dmas = <&blsp_dma 14>, <&blsp_dma 15>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
...@@ -333,9 +333,9 @@ i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ ...@@ -333,9 +333,9 @@ i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */
#size-cells = <0>; #size-cells = <0>;
reg = <0x0 0x078b7000 0x0 0x600>; reg = <0x0 0x078b7000 0x0 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clock-frequency = <400000>; clock-frequency = <400000>;
dmas = <&blsp_dma 16>, <&blsp_dma 17>; dmas = <&blsp_dma 16>, <&blsp_dma 17>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
......
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View file @ 2374b99e
...@@ -467,9 +467,9 @@ blsp1_i2c2: i2c@78b6000 { ...@@ -467,9 +467,9 @@ blsp1_i2c2: i2c@78b6000 {
#size-cells = <0>; #size-cells = <0>;
reg = <0x078b6000 0x600>; reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clock-frequency = <400000>; clock-frequency = <400000>;
dmas = <&blsp_dma 14>, <&blsp_dma 15>; dmas = <&blsp_dma 14>, <&blsp_dma 15>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
...@@ -484,9 +484,9 @@ blsp1_i2c3: i2c@78b7000 { ...@@ -484,9 +484,9 @@ blsp1_i2c3: i2c@78b7000 {
#size-cells = <0>; #size-cells = <0>;
reg = <0x078b7000 0x600>; reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clock-frequency = <100000>; clock-frequency = <100000>;
dmas = <&blsp_dma 16>, <&blsp_dma 17>; dmas = <&blsp_dma 16>, <&blsp_dma 17>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
...@@ -499,9 +499,9 @@ blsp1_i2c5: i2c@78b9000 { ...@@ -499,9 +499,9 @@ blsp1_i2c5: i2c@78b9000 {
#size-cells = <0>; #size-cells = <0>;
reg = <0x78b9000 0x600>; reg = <0x78b9000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clock-frequency = <400000>; clock-frequency = <400000>;
dmas = <&blsp_dma 20>, <&blsp_dma 21>; dmas = <&blsp_dma 20>, <&blsp_dma 21>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
...@@ -514,9 +514,9 @@ blsp1_i2c6: i2c@78ba000 { ...@@ -514,9 +514,9 @@ blsp1_i2c6: i2c@78ba000 {
#size-cells = <0>; #size-cells = <0>;
reg = <0x078ba000 0x600>; reg = <0x078ba000 0x600>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clock-frequency = <100000>; clock-frequency = <100000>;
dmas = <&blsp_dma 22>, <&blsp_dma 23>; dmas = <&blsp_dma 22>, <&blsp_dma 23>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
......
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file @ 2374b99e
...@@ -1511,9 +1511,9 @@ blsp_i2c1: i2c@78b5000 { ...@@ -1511,9 +1511,9 @@ blsp_i2c1: i2c@78b5000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b5000 0x500>; reg = <0x078b5000 0x500>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_default>; pinctrl-0 = <&i2c1_default>;
pinctrl-1 = <&i2c1_sleep>; pinctrl-1 = <&i2c1_sleep>;
...@@ -1543,9 +1543,9 @@ blsp_i2c2: i2c@78b6000 { ...@@ -1543,9 +1543,9 @@ blsp_i2c2: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b6000 0x500>; reg = <0x078b6000 0x500>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_default>; pinctrl-0 = <&i2c2_default>;
pinctrl-1 = <&i2c2_sleep>; pinctrl-1 = <&i2c2_sleep>;
...@@ -1575,9 +1575,9 @@ blsp_i2c3: i2c@78b7000 { ...@@ -1575,9 +1575,9 @@ blsp_i2c3: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b7000 0x500>; reg = <0x078b7000 0x500>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c3_default>; pinctrl-0 = <&i2c3_default>;
pinctrl-1 = <&i2c3_sleep>; pinctrl-1 = <&i2c3_sleep>;
...@@ -1607,9 +1607,9 @@ blsp_i2c4: i2c@78b8000 { ...@@ -1607,9 +1607,9 @@ blsp_i2c4: i2c@78b8000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b8000 0x500>; reg = <0x078b8000 0x500>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c4_default>; pinctrl-0 = <&i2c4_default>;
pinctrl-1 = <&i2c4_sleep>; pinctrl-1 = <&i2c4_sleep>;
...@@ -1639,9 +1639,9 @@ blsp_i2c5: i2c@78b9000 { ...@@ -1639,9 +1639,9 @@ blsp_i2c5: i2c@78b9000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b9000 0x500>; reg = <0x078b9000 0x500>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_default>; pinctrl-0 = <&i2c5_default>;
pinctrl-1 = <&i2c5_sleep>; pinctrl-1 = <&i2c5_sleep>;
...@@ -1671,9 +1671,9 @@ blsp_i2c6: i2c@78ba000 { ...@@ -1671,9 +1671,9 @@ blsp_i2c6: i2c@78ba000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078ba000 0x500>; reg = <0x078ba000 0x500>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c6_default>; pinctrl-0 = <&i2c6_default>;
pinctrl-1 = <&i2c6_sleep>; pinctrl-1 = <&i2c6_sleep>;
......
arch/arm64/boot/dts/qcom/msm8953.dtsi
View file @ 2374b99e
...@@ -923,9 +923,9 @@ i2c_1: i2c@78b5000 { ...@@ -923,9 +923,9 @@ i2c_1: i2c@78b5000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b5000 0x600>; reg = <0x78b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_1_default>; pinctrl-0 = <&i2c_1_default>;
...@@ -941,9 +941,9 @@ i2c_2: i2c@78b6000 { ...@@ -941,9 +941,9 @@ i2c_2: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b6000 0x600>; reg = <0x78b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_2_default>; pinctrl-0 = <&i2c_2_default>;
...@@ -959,9 +959,9 @@ i2c_3: i2c@78b7000 { ...@@ -959,9 +959,9 @@ i2c_3: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b7000 0x600>; reg = <0x78b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_3_default>; pinctrl-0 = <&i2c_3_default>;
pinctrl-1 = <&i2c_3_sleep>; pinctrl-1 = <&i2c_3_sleep>;
...@@ -976,9 +976,9 @@ i2c_4: i2c@78b8000 { ...@@ -976,9 +976,9 @@ i2c_4: i2c@78b8000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b8000 0x600>; reg = <0x78b8000 0x600>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_4_default>; pinctrl-0 = <&i2c_4_default>;
pinctrl-1 = <&i2c_4_sleep>; pinctrl-1 = <&i2c_4_sleep>;
...@@ -993,9 +993,9 @@ i2c_5: i2c@7af5000 { ...@@ -993,9 +993,9 @@ i2c_5: i2c@7af5000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x7af5000 0x600>; reg = <0x7af5000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_AHB_CLK>, clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; <&gcc GCC_BLSP2_AHB_CLK>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_5_default>; pinctrl-0 = <&i2c_5_default>;
pinctrl-1 = <&i2c_5_sleep>; pinctrl-1 = <&i2c_5_sleep>;
...@@ -1010,9 +1010,9 @@ i2c_6: i2c@7af6000 { ...@@ -1010,9 +1010,9 @@ i2c_6: i2c@7af6000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x7af6000 0x600>; reg = <0x7af6000 0x600>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_AHB_CLK>, clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; <&gcc GCC_BLSP2_AHB_CLK>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_6_default>; pinctrl-0 = <&i2c_6_default>;
pinctrl-1 = <&i2c_6_sleep>; pinctrl-1 = <&i2c_6_sleep>;
...@@ -1027,9 +1027,9 @@ i2c_7: i2c@7af7000 { ...@@ -1027,9 +1027,9 @@ i2c_7: i2c@7af7000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x7af7000 0x600>; reg = <0x7af7000 0x600>;
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_AHB_CLK>, clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>; <&gcc GCC_BLSP2_AHB_CLK>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_7_default>; pinctrl-0 = <&i2c_7_default>;
pinctrl-1 = <&i2c_7_sleep>; pinctrl-1 = <&i2c_7_sleep>;
...@@ -1044,9 +1044,9 @@ i2c_8: i2c@7af8000 { ...@@ -1044,9 +1044,9 @@ i2c_8: i2c@7af8000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x7af8000 0x600>; reg = <0x7af8000 0x600>;
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_AHB_CLK>, clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>; <&gcc GCC_BLSP2_AHB_CLK>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_8_default>; pinctrl-0 = <&i2c_8_default>;
pinctrl-1 = <&i2c_8_sleep>; pinctrl-1 = <&i2c_8_sleep>;
......
arch/arm64/boot/dts/qcom/msm8994.dtsi
View file @ 2374b99e
...@@ -519,9 +519,9 @@ blsp1_i2c1: i2c@f9923000 { ...@@ -519,9 +519,9 @@ blsp1_i2c1: i2c@f9923000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9923000 0x500>; reg = <0xf9923000 0x500>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clock-frequency = <400000>; clock-frequency = <400000>;
dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
...@@ -555,9 +555,9 @@ blsp1_i2c2: i2c@f9924000 { ...@@ -555,9 +555,9 @@ blsp1_i2c2: i2c@f9924000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9924000 0x500>; reg = <0xf9924000 0x500>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clock-frequency = <400000>; clock-frequency = <400000>;
dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
...@@ -575,9 +575,9 @@ blsp1_i2c4: i2c@f9926000 { ...@@ -575,9 +575,9 @@ blsp1_i2c4: i2c@f9926000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9926000 0x500>; reg = <0xf9926000 0x500>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clock-frequency = <400000>; clock-frequency = <400000>;
dmas = <&blsp1_dma 18>, <&blsp1_dma 19>; dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
...@@ -593,9 +593,9 @@ blsp1_i2c5: i2c@f9927000 { ...@@ -593,9 +593,9 @@ blsp1_i2c5: i2c@f9927000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9927000 0x500>; reg = <0xf9927000 0x500>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clock-frequency = <400000>; clock-frequency = <400000>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
...@@ -611,9 +611,9 @@ blsp1_i2c6: i2c@f9928000 { ...@@ -611,9 +611,9 @@ blsp1_i2c6: i2c@f9928000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9928000 0x500>; reg = <0xf9928000 0x500>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clock-frequency = <400000>; clock-frequency = <400000>;
dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
...@@ -657,9 +657,9 @@ blsp2_i2c1: i2c@f9963000 { ...@@ -657,9 +657,9 @@ blsp2_i2c1: i2c@f9963000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9963000 0x500>; reg = <0xf9963000 0x500>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>, clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clock-frequency = <400000>; clock-frequency = <400000>;
dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
...@@ -693,9 +693,9 @@ blsp2_i2c5: i2c@f9967000 { ...@@ -693,9 +693,9 @@ blsp2_i2c5: i2c@f9967000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9967000 0x500>; reg = <0xf9967000 0x500>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>, clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clock-frequency = <355000>; clock-frequency = <355000>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
......
arch/arm64/boot/dts/qcom/msm8996.dtsi
View file @ 2374b99e
...@@ -2787,9 +2787,9 @@ blsp1_i2c3: i2c@7577000 { ...@@ -2787,9 +2787,9 @@ blsp1_i2c3: i2c@7577000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07577000 0x1000>; reg = <0x07577000 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c3_default>; pinctrl-0 = <&blsp1_i2c3_default>;
pinctrl-1 = <&blsp1_i2c3_sleep>; pinctrl-1 = <&blsp1_i2c3_sleep>;
...@@ -2835,9 +2835,9 @@ blsp2_i2c1: i2c@75b5000 { ...@@ -2835,9 +2835,9 @@ blsp2_i2c1: i2c@75b5000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b5000 0x1000>; reg = <0x075b5000 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>, clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c1_default>; pinctrl-0 = <&blsp2_i2c1_default>;
pinctrl-1 = <&blsp2_i2c1_sleep>; pinctrl-1 = <&blsp2_i2c1_sleep>;
...@@ -2852,9 +2852,9 @@ blsp2_i2c2: i2c@75b6000 { ...@@ -2852,9 +2852,9 @@ blsp2_i2c2: i2c@75b6000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b6000 0x1000>; reg = <0x075b6000 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>, clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c2_default>; pinctrl-0 = <&blsp2_i2c2_default>;
pinctrl-1 = <&blsp2_i2c2_sleep>; pinctrl-1 = <&blsp2_i2c2_sleep>;
...@@ -2869,9 +2869,9 @@ blsp2_i2c3: i2c@75b7000 { ...@@ -2869,9 +2869,9 @@ blsp2_i2c3: i2c@75b7000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b7000 0x1000>; reg = <0x075b7000 0x1000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>, clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>; <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c3_default>; pinctrl-0 = <&blsp2_i2c3_default>;
...@@ -2887,9 +2887,9 @@ blsp2_i2c5: i2c@75b9000 { ...@@ -2887,9 +2887,9 @@ blsp2_i2c5: i2c@75b9000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x75b9000 0x1000>; reg = <0x75b9000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>, clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&blsp2_i2c5_default>; pinctrl-0 = <&blsp2_i2c5_default>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
...@@ -2903,9 +2903,9 @@ blsp2_i2c6: i2c@75ba000 { ...@@ -2903,9 +2903,9 @@ blsp2_i2c6: i2c@75ba000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x75ba000 0x1000>; reg = <0x75ba000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>, clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>; <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c6_default>; pinctrl-0 = <&blsp2_i2c6_default>;
pinctrl-1 = <&blsp2_i2c6_sleep>; pinctrl-1 = <&blsp2_i2c6_sleep>;
......
arch/arm64/boot/dts/qcom/qcs404.dtsi
View file @ 2374b99e
...@@ -914,9 +914,9 @@ blsp1_i2c0: i2c@78b5000 { ...@@ -914,9 +914,9 @@ blsp1_i2c0: i2c@78b5000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b5000 0x600>; reg = <0x078b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c0_default>; pinctrl-0 = <&blsp1_i2c0_default>;
#address-cells = <1>; #address-cells = <1>;
...@@ -928,9 +928,9 @@ blsp1_spi0: spi@78b5000 { ...@@ -928,9 +928,9 @@ blsp1_spi0: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1"; compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b5000 0x600>; reg = <0x078b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&blsp1_spi0_default>; pinctrl-0 = <&blsp1_spi0_default>;
#address-cells = <1>; #address-cells = <1>;
...@@ -942,9 +942,9 @@ blsp1_i2c1: i2c@78b6000 { ...@@ -942,9 +942,9 @@ blsp1_i2c1: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b6000 0x600>; reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c1_default>; pinctrl-0 = <&blsp1_i2c1_default>;
#address-cells = <1>; #address-cells = <1>;
...@@ -956,9 +956,9 @@ blsp1_spi1: spi@78b6000 { ...@@ -956,9 +956,9 @@ blsp1_spi1: spi@78b6000 {
compatible = "qcom,spi-qup-v2.2.1"; compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b6000 0x600>; reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&blsp1_spi1_default>; pinctrl-0 = <&blsp1_spi1_default>;
#address-cells = <1>; #address-cells = <1>;
...@@ -970,9 +970,9 @@ blsp1_i2c2: i2c@78b7000 { ...@@ -970,9 +970,9 @@ blsp1_i2c2: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b7000 0x600>; reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c2_default>; pinctrl-0 = <&blsp1_i2c2_default>;
#address-cells = <1>; #address-cells = <1>;
...@@ -984,9 +984,9 @@ blsp1_spi2: spi@78b7000 { ...@@ -984,9 +984,9 @@ blsp1_spi2: spi@78b7000 {
compatible = "qcom,spi-qup-v2.2.1"; compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b7000 0x600>; reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&blsp1_spi2_default>; pinctrl-0 = <&blsp1_spi2_default>;
#address-cells = <1>; #address-cells = <1>;
...@@ -998,9 +998,9 @@ blsp1_i2c3: i2c@78b8000 { ...@@ -998,9 +998,9 @@ blsp1_i2c3: i2c@78b8000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b8000 0x600>; reg = <0x078b8000 0x600>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c3_default>; pinctrl-0 = <&blsp1_i2c3_default>;
#address-cells = <1>; #address-cells = <1>;
...@@ -1012,9 +1012,9 @@ blsp1_spi3: spi@78b8000 { ...@@ -1012,9 +1012,9 @@ blsp1_spi3: spi@78b8000 {
compatible = "qcom,spi-qup-v2.2.1"; compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b8000 0x600>; reg = <0x078b8000 0x600>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&blsp1_spi3_default>; pinctrl-0 = <&blsp1_spi3_default>;
#address-cells = <1>; #address-cells = <1>;
...@@ -1026,9 +1026,9 @@ blsp1_i2c4: i2c@78b9000 { ...@@ -1026,9 +1026,9 @@ blsp1_i2c4: i2c@78b9000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b9000 0x600>; reg = <0x078b9000 0x600>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c4_default>; pinctrl-0 = <&blsp1_i2c4_default>;
#address-cells = <1>; #address-cells = <1>;
...@@ -1040,9 +1040,9 @@ blsp1_spi4: spi@78b9000 { ...@@ -1040,9 +1040,9 @@ blsp1_spi4: spi@78b9000 {
compatible = "qcom,spi-qup-v2.2.1"; compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b9000 0x600>; reg = <0x078b9000 0x600>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&blsp1_spi4_default>; pinctrl-0 = <&blsp1_spi4_default>;
#address-cells = <1>; #address-cells = <1>;
...@@ -1078,9 +1078,9 @@ blsp2_i2c0: i2c@7af5000 { ...@@ -1078,9 +1078,9 @@ blsp2_i2c0: i2c@7af5000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07af5000 0x600>; reg = <0x07af5000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>, clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>; <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&blsp2_i2c0_default>; pinctrl-0 = <&blsp2_i2c0_default>;
#address-cells = <1>; #address-cells = <1>;
...@@ -1092,9 +1092,9 @@ blsp2_spi0: spi@7af5000 { ...@@ -1092,9 +1092,9 @@ blsp2_spi0: spi@7af5000 {
compatible = "qcom,spi-qup-v2.2.1"; compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07af5000 0x600>; reg = <0x07af5000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>, clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>,
<&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>; <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "iface", "core"; clock-names = "core", "iface";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&blsp2_spi0_default>; pinctrl-0 = <&blsp2_spi0_default>;
#address-cells = <1>; #address-cells = <1>;
......
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